ipq40xx: fix AP-303H PSE GPIO pin

The GPIO chip is at a different start index compared to OpenWrt master.

Signed-off-by: David Bauer <mail@david-bauer.net>

diff --git a/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches b/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches
index f57d4c5888881772d0e228387d46fdb13191e025..fcc6e8e745639ed2c8fa4dfd7fe36f998efb017e 100644 (file)
--- a/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches
+++ b/target/linux/ipq40xx/base-files/etc/board.d/03_gpio_switches
@@ -7,7 +7,7 @@ board=$(board_name)
 
 case "$board" in
 aruba,ap-303h)
-       ucidef_add_gpio_switch "poe_passtrough" "POE passtrough disable" "546" "1"
+       ucidef_add_gpio_switch "poe_passtrough" "POE passtrough disable" "446" "1"
        ;;
 cellc,rtl30vw)
        ucidef_add_gpio_switch "w_disable" "W_DISABLE mPCIE pin" "398" "1"