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+ Wed, 21 Nov 2018 10:31:40 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 01/17] ARM: add CONFIG_ARCH_SUNXI_V7 for differentiate
+ ARMv5/v7 Allwinner SoCs
+Date: Wed, 21 Nov 2018 21:30:34 +0300
+Message-Id:
+ <267ffcf3b91930a82f20d93e1fad1fceaf8b9b0e.1542824904.git.mesihkilinc@gmail.com>
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+
+Allwinner also has some ARMv5 SoCs.
+
+In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config
+which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI
+a common option which is selected by both V7 and V5 sunxi option.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+---
+ arch/arm/mach-sunxi/Kconfig | 23 ++++++++++++++++-------
+ 1 file changed, 16 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index d9c8ecf..7e5f173 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -6,31 +6,38 @@ menuconfig ARCH_SUNXI
+ select GENERIC_IRQ_CHIP
+ select GPIOLIB
+ select PINCTRL
+- select PM_OPP
+ select SUN4I_TIMER
+ select RESET_CONTROLLER
++ help
++ Support for Allwinner ARM-based family of processors
+
+ if ARCH_SUNXI
+
++if ARCH_MULTI_V7
++
++config ARCH_SUNXI_V7
++ bool
++ select PM_OPP
++
+ config MACH_SUN4I
+ bool "Allwinner A10 (sun4i) SoCs support"
+- default ARCH_SUNXI
++ select ARCH_SUNXI_V7
+
+ config MACH_SUN5I
+ bool "Allwinner A10s / A13 (sun5i) SoCs support"
+- default ARCH_SUNXI
++ select ARCH_SUNXI_V7
+ select SUN5I_HSTIMER
+
+ config MACH_SUN6I
+ bool "Allwinner A31 (sun6i) SoCs support"
+- default ARCH_SUNXI
++ select ARCH_SUNXI_V7
+ select ARM_GIC
+ select MFD_SUN6I_PRCM
+ select SUN5I_HSTIMER
+
+ config MACH_SUN7I
+ bool "Allwinner A20 (sun7i) SoCs support"
+- default ARCH_SUNXI
++ select ARCH_SUNXI_V7
+ select ARM_GIC
+ select ARM_PSCI
+ select ARCH_SUPPORTS_BIG_ENDIAN
+@@ -39,13 +46,13 @@ config MACH_SUN7I
+
+ config MACH_SUN8I
+ bool "Allwinner sun8i Family SoCs support"
+- default ARCH_SUNXI
++ select ARCH_SUNXI_V7
+ select ARM_GIC
+ select MFD_SUN6I_PRCM
+
+ config MACH_SUN9I
+ bool "Allwinner (sun9i) SoCs support"
+- default ARCH_SUNXI
++ select ARCH_SUNXI_V7
+ select ARM_GIC
+
+ config ARCH_SUNXI_MC_SMP
+@@ -56,3 +63,5 @@ config ARCH_SUNXI_MC_SMP
+ select ARM_CPU_SUSPEND
+
+ endif
++
++endif
+
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+ Wed, 21 Nov 2018 10:31:45 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 03/17] ARM: sunxi: add Allwinner ARMv5 SoCs
+Date: Wed, 21 Nov 2018 21:30:36 +0300
+Message-Id:
+ <731846a31ad2c602ca4fcf1c417deace60c625b8.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+Sender: linux-clk-owner@vger.kernel.org
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+
+Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
+used for many new F-series products, including F1C100A, F1C100s, F1C200s,
+F1C500, F1C600).
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ arch/arm/mach-sunxi/Kconfig | 16 +++++++++++++++-
+ arch/arm/mach-sunxi/sunxi.c | 10 ++++++++++
+ 2 files changed, 25 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index 7e5f173..23dffbd 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -1,6 +1,6 @@
+ menuconfig ARCH_SUNXI
+ bool "Allwinner SoCs"
+- depends on ARCH_MULTI_V7
++ depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
+ select ARCH_HAS_RESET_CONTROLLER
+ select CLKSRC_MMIO
+ select GENERIC_IRQ_CHIP
+@@ -64,4 +64,18 @@ config ARCH_SUNXI_MC_SMP
+
+ endif
+
++if ARCH_MULTI_V5
++
++config ARCH_SUNXI_V5
++ bool
++
++config MACH_SUNIV
++ bool "Allwinner ARMv5 F-series (suniv) SoCs support"
++ select ARCH_SUNXI_V5
++ help
++ Support for Allwinner suniv ARMv5 SoCs.
++ (F1C100A, F1C100s, F1C200s, F1C500, F1C600)
++
++endif
++
+ endif
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index de4b0e9..155cd9e 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -101,3 +101,13 @@ static const char * const sun9i_board_dt_compat[] = {
+ DT_MACHINE_START(SUN9I_DT, "Allwinner sun9i Family")
+ .dt_compat = sun9i_board_dt_compat,
+ MACHINE_END
++
++static const char * const suniv_board_dt_compat[] = {
++ "allwinner,suniv-f1c100s",
++ NULL,
++};
++
++DT_MACHINE_START(SUNIV_DT, "Allwinner suniv Family")
++ .dt_compat = suniv_board_dt_compat,
++MACHINE_END
++
+
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+ Wed, 21 Nov 2018 10:31:47 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 04/17] dt-bindings: interrupt-controller: Add suniv
+ interrupt-controller
+Date: Wed, 21 Nov 2018 21:30:37 +0300
+Message-Id:
+ <d0942fe5b1bb83646af0fa1f475ac0b468e1612e.1542824904.git.mesihkilinc@gmail.com>
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+
+Add compatible string for Alwinner suniv F1C100s SoC interrupt
+controller which is stripped version of sun4i
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ .../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+index b290ca1..4043525 100644
+--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
++++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+@@ -2,7 +2,9 @@ Allwinner Sunxi Interrupt Controller
+
+ Required properties:
+
+-- compatible : should be "allwinner,sun4i-a10-ic"
++- compatible : should be one of the following:
++ "allwinner,sun4i-a10-ic"
++ "allwinner,suniv-f1c100s-ic"
+ - reg : Specifies base physical address and size of the registers.
+ - interrupt-controller : Identifies the node as an interrupt controller
+ - #interrupt-cells : Specifies the number of cells needed to encode an
+
+From patchwork Wed Nov 21 18:30:38 2018
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+X-Patchwork-Id: 10692993
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+ Wed, 21 Nov 2018 10:31:49 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 05/17] irqchip/sun4i: add support for suniv interrupt
+ controller
+Date: Wed, 21 Nov 2018 21:30:38 +0300
+Message-Id:
+ <08b40429e46626f4caf8e4d2287b5c4d354e3b7f.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
+In-Reply-To: <cover.1542824904.git.mesihkilinc@gmail.com>
+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
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+List-ID: <linux-clk.vger.kernel.org>
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+
+The new F-series SoCs (suniv) from Allwinner use an stripped version of
+the interrupt controller in A10/A13
+
+Add support for it in irq-sun4i driver.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+---
+ drivers/irqchip/irq-sun4i.c | 104 +++++++++++++++++++++++++++++++-------------
+ 1 file changed, 74 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
+index e3e5b91..7ca4a4d 100644
+--- a/drivers/irqchip/irq-sun4i.c
++++ b/drivers/irqchip/irq-sun4i.c
+@@ -28,11 +28,21 @@
+ #define SUN4I_IRQ_NMI_CTRL_REG 0x0c
+ #define SUN4I_IRQ_PENDING_REG(x) (0x10 + 0x4 * x)
+ #define SUN4I_IRQ_FIQ_PENDING_REG(x) (0x20 + 0x4 * x)
+-#define SUN4I_IRQ_ENABLE_REG(x) (0x40 + 0x4 * x)
+-#define SUN4I_IRQ_MASK_REG(x) (0x50 + 0x4 * x)
++#define SUN4I_IRQ_ENABLE_REG(x) (irq_ic_data->enable_req_offset + 0x4 * x)
++#define SUN4I_IRQ_MASK_REG(x) (irq_ic_data->mask_req_offset + 0x4 * x)
++#define SUN4I_IRQ_ENABLE_REG_OFFSET 0x40
++#define SUN4I_IRQ_MASK_REG_OFFSET 0x50
++#define SUNIV_IRQ_ENABLE_REG_OFFSET 0x20
++#define SUNIV_IRQ_MASK_REG_OFFSET 0x30
++
++struct sunxi_irq_chip_data{
++ void __iomem *irq_base;
++ struct irq_domain *irq_domain;
++ u32 enable_req_offset;
++ u32 mask_req_offset;
++};
+
+-static void __iomem *sun4i_irq_base;
+-static struct irq_domain *sun4i_irq_domain;
++static struct sunxi_irq_chip_data *irq_ic_data;
+
+ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
+
+@@ -43,7 +53,7 @@ static void sun4i_irq_ack(struct irq_data *irqd)
+ if (irq != 0)
+ return; /* Only IRQ 0 / the ENMI needs to be acked */
+
+- writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
++ writel(BIT(0), irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
+ }
+
+ static void sun4i_irq_mask(struct irq_data *irqd)
+@@ -53,9 +63,9 @@ static void sun4i_irq_mask(struct irq_data *irqd)
+ int reg = irq / 32;
+ u32 val;
+
+- val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
++ val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+ writel(val & ~(1 << irq_off),
+- sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
++ irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+ }
+
+ static void sun4i_irq_unmask(struct irq_data *irqd)
+@@ -65,9 +75,9 @@ static void sun4i_irq_unmask(struct irq_data *irqd)
+ int reg = irq / 32;
+ u32 val;
+
+- val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
++ val = readl(irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+ writel(val | (1 << irq_off),
+- sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
++ irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+ }
+
+ static struct irq_chip sun4i_irq_chip = {
+@@ -95,42 +105,76 @@ static const struct irq_domain_ops sun4i_irq_ops = {
+ static int __init sun4i_of_init(struct device_node *node,
+ struct device_node *parent)
+ {
+- sun4i_irq_base = of_iomap(node, 0);
+- if (!sun4i_irq_base)
++ irq_ic_data->irq_base = of_iomap(node, 0);
++ if (!irq_ic_data->irq_base)
+ panic("%pOF: unable to map IC registers\n",
+ node);
+
+ /* Disable all interrupts */
+- writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
+- writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
+- writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
++ writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(0));
++ writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(1));
++ writel(0, irq_ic_data->irq_base + SUN4I_IRQ_ENABLE_REG(2));
+
+ /* Unmask all the interrupts, ENABLE_REG(x) is used for masking */
+- writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
+- writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
+- writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
++ writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(0));
++ writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(1));
++ writel(0, irq_ic_data->irq_base + SUN4I_IRQ_MASK_REG(2));
+
+ /* Clear all the pending interrupts */
+- writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
+- writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
+- writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
++ writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0));
++ writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(1));
++ writel(0xffffffff, irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(2));
+
+- /* Enable protection mode */
+- writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
++ /* Enable protection mode (not available in suniv) */
++ if (of_device_is_compatible(node, "allwinner,sun4i-a10-ic"))
++ writel(0x01, irq_ic_data->irq_base + SUN4I_IRQ_PROTECTION_REG);
+
+ /* Configure the external interrupt source type */
+- writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
++ writel(0x00, irq_ic_data->irq_base + SUN4I_IRQ_NMI_CTRL_REG);
+
+- sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
++ irq_ic_data->irq_domain = irq_domain_add_linear(node, 3 * 32,
+ &sun4i_irq_ops, NULL);
+- if (!sun4i_irq_domain)
++ if (!irq_ic_data->irq_domain)
+ panic("%pOF: unable to create IRQ domain\n", node);
+
+ set_handle_irq(sun4i_handle_irq);
+
+ return 0;
+ }
+-IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_of_init);
++
++static int __init sun4i_ic_of_init(struct device_node *node,
++ struct device_node *parent)
++{
++ irq_ic_data = kzalloc(sizeof(struct sunxi_irq_chip_data), GFP_KERNEL);
++ if (!irq_ic_data) {
++ pr_err("kzalloc failed!\n");
++ return -ENOMEM;
++ }
++
++ irq_ic_data->enable_req_offset = SUN4I_IRQ_ENABLE_REG_OFFSET;
++ irq_ic_data->mask_req_offset = SUN4I_IRQ_MASK_REG_OFFSET;
++
++ return sun4i_of_init(node, parent);
++}
++
++IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-a10-ic", sun4i_ic_of_init);
++
++static int __init suniv_ic_of_init(struct device_node *node,
++ struct device_node *parent)
++{
++ irq_ic_data = kzalloc(sizeof(struct sunxi_irq_chip_data), GFP_KERNEL);
++ if (!irq_ic_data) {
++ pr_err("kzalloc failed!\n");
++ return -ENOMEM;
++ }
++
++ irq_ic_data->enable_req_offset = SUNIV_IRQ_ENABLE_REG_OFFSET;
++ irq_ic_data->mask_req_offset = SUNIV_IRQ_MASK_REG_OFFSET;
++
++ return sun4i_of_init(node, parent);
++}
++
++IRQCHIP_DECLARE(allwinner_sunvi_ic, "allwinner,suniv-f1c100s-ic", suniv_ic_of_init);
+
+ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
+ {
+@@ -146,13 +190,13 @@ static void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
+ * the extra check in the common case of 1 hapening after having
+ * read the vector-reg once.
+ */
+- hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
++ hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+ if (hwirq == 0 &&
+- !(readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
++ !(readl(irq_ic_data->irq_base + SUN4I_IRQ_PENDING_REG(0)) & BIT(0)))
+ return;
+
+ do {
+- handle_domain_irq(sun4i_irq_domain, hwirq, regs);
+- hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
++ handle_domain_irq(irq_ic_data->irq_domain, hwirq, regs);
++ hwirq = readl(irq_ic_data->irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+ } while (hwirq != 0);
+ }
+
+From patchwork Wed Nov 21 18:30:39 2018
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+ Wed, 21 Nov 2018 10:31:52 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 06/17] dt-bindings: timer: Add Allwinner suniv timer
+Date: Wed, 21 Nov 2018 21:30:39 +0300
+Message-Id:
+ <9927bde09ef20cadccdf81541fd1f91165508357.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+Sender: linux-clk-owner@vger.kernel.org
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+
+Add compatible string for Allwinner suniv timer which is similar to
+sun4i timer.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+index 5c2e235..3da9d51 100644
+--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
++++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+@@ -2,7 +2,9 @@ Allwinner A1X SoCs Timer Controller
+
+ Required properties:
+
+-- compatible : should be "allwinner,sun4i-a10-timer"
++- compatible : should be one of the following:
++ "allwinner,sun4i-a10-timer"
++ "allwinner,suniv-f1c100s-timer"
+ - reg : Specifies base physical address and size of the registers.
+ - interrupts : The interrupt of the first timer
+ - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
+
+From patchwork Wed Nov 21 18:30:40 2018
+Content-Type: text/plain; charset="utf-8"
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+X-Patchwork-Submitter: Mesih Kilinc <mesihkilinc@gmail.com>
+X-Patchwork-Id: 10692987
+Return-Path: <linux-clk-owner@kernel.org>
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+ Wed, 21 Nov 2018 10:31:54 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 07/17] clocksource: sun4i: add a compatible for suniv
+Date: Wed, 21 Nov 2018 21:30:40 +0300
+Message-Id:
+ <60bc70fc43743f664de76abf3ab0a01cd7924458.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+
+The suniv (new F-series) chip has a timer with less functionality than
+the A10 timer, e.g. it has only 3 channels.
+
+Add a new compatible for it. As we didn't use the extra channels on A10
+either now, the code needn't to be changed.
+
+The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer.
+
+Register sun4i_timer as sched_clock on it.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ drivers/clocksource/sun4i_timer.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
+index 6e0180a..65f38f6 100644
+--- a/drivers/clocksource/sun4i_timer.c
++++ b/drivers/clocksource/sun4i_timer.c
+@@ -186,7 +186,8 @@ static int __init sun4i_timer_init(struct device_node *node)
+ */
+ if (of_machine_is_compatible("allwinner,sun4i-a10") ||
+ of_machine_is_compatible("allwinner,sun5i-a13") ||
+- of_machine_is_compatible("allwinner,sun5i-a10s"))
++ of_machine_is_compatible("allwinner,sun5i-a10s") ||
++ of_machine_is_compatible("allwinner,suniv-f1c100s"))
+ sched_clock_register(sun4i_timer_sched_read, 32,
+ timer_of_rate(&to));
+
+@@ -218,3 +219,5 @@ static int __init sun4i_timer_init(struct device_node *node)
+ }
+ TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
+ sun4i_timer_init);
++TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
++ sun4i_timer_init);
+
+From patchwork Wed Nov 21 18:30:41 2018
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+ Wed, 21 Nov 2018 10:31:56 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 08/17] dt-bindings: pinctrl: Add Allwinner suniv
+ F1C100s pinctrl
+Date: Wed, 21 Nov 2018 21:30:41 +0300
+Message-Id:
+ <70ac024bf3b6623dc41021ac4893c37adb85a97d.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+List-ID: <linux-clk.vger.kernel.org>
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+
+Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+index 258a464..a7f7133 100644
+--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
++++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+@@ -29,6 +29,7 @@ Required properties:
+ "allwinner,sun50i-h5-pinctrl"
+ "allwinner,sun50i-h6-pinctrl"
+ "allwinner,sun50i-h6-r-pinctrl"
++ "allwinner,suniv-f1c100s-pinctrl"
+ "nextthing,gr8-pinctrl"
+
+ - reg: Should contain the register physical address and length for the
+
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+ Wed, 21 Nov 2018 10:31:58 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 09/17] pinctrl: sunxi: add support for suniv F1C100s
+ (newer F-series SoCs)
+Date: Wed, 21 Nov 2018 21:30:42 +0300
+Message-Id:
+ <fc20d96f5531d7d1eb5ce3d5cf920c8bf59cad58.1542824904.git.mesihkilinc@gmail.com>
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+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-clk.vger.kernel.org>
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+
+The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
+pin
+controller like other SoCs from Allwinner.
+
+Add support for it.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ drivers/pinctrl/sunxi/Kconfig | 4 +
+ drivers/pinctrl/sunxi/Makefile | 1 +
+ drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c | 417 ++++++++++++++++++++++++++
+ 3 files changed, 422 insertions(+)
+ create mode 100644 drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
+
+diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
+index 95282cd..a731fc9 100644
+--- a/drivers/pinctrl/sunxi/Kconfig
++++ b/drivers/pinctrl/sunxi/Kconfig
+@@ -6,6 +6,10 @@ config PINCTRL_SUNXI
+ select GENERIC_PINCONF
+ select GPIOLIB
+
++config PINCTRL_SUNIV_F1C100S
++ def_bool MACH_SUNIV
++ select PINCTRL_SUNXI
++
+ config PINCTRL_SUN4I_A10
+ def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
+ select PINCTRL_SUNXI
+diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
+index adb8443..fafcdae 100644
+--- a/drivers/pinctrl/sunxi/Makefile
++++ b/drivers/pinctrl/sunxi/Makefile
+@@ -3,6 +3,7 @@
+ obj-y += pinctrl-sunxi.o
+
+ # SoC Drivers
++obj-$(CONFIG_PINCTRL_SUNIV_F1C100S) += pinctrl-suniv-f1c100s.o
+ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o
+ obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o
+ obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o
+diff --git a/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
+new file mode 100644
+index 0000000..46d5667
+--- /dev/null
++++ b/drivers/pinctrl/sunxi/pinctrl-suniv-f1c100s.c
+@@ -0,0 +1,417 @@
++/*
++ * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver.
++ *
++ * Copyright (C) 2018 Icenowy Zheng
++ *
++ * Icenowy Zheng <icenowy@aosc.io>
++ *
++ * Copyright (C) 2014 Jackie Hwang
++ *
++ * Jackie Hwang <huangshr@allwinnertech.com>
++ *
++ * Copyright (C) 2014 Chen-Yu Tsai
++ *
++ * Chen-Yu Tsai <wens@csie.org>
++ *
++ * Copyright (C) 2014 Maxime Ripard
++ *
++ * Maxime Ripard <maxime.ripard@free-electrons.com>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/pinctrl/pinctrl.h>
++
++#include "pinctrl-sunxi.h"
++static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "rtp"), /* X1 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
++ SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
++ SUNXI_FUNCTION(0x6, "spi1")), /* CS */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "rtp"), /* X2 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
++ SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
++ SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "rtp"), /* Y1 */
++ SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* IN */
++ SUNXI_FUNCTION(0x5, "uart1"), /* RX */
++ SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "rtp"), /* Y2 */
++ SUNXI_FUNCTION(0x3, "ir0"), /* RX */
++ SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
++ SUNXI_FUNCTION(0x5, "uart1"), /* TX */
++ SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "dram"), /* DQS0 */
++ SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
++ SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
++ SUNXI_FUNCTION(0x5, "uart1"), /* RTS */
++ SUNXI_FUNCTION(0x6, "spi1")), /* CS */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "dram"), /* DQS1 */
++ SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
++ SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
++ SUNXI_FUNCTION(0x5, "uart1"), /* CTS */
++ SUNXI_FUNCTION(0x6, "spi1")), /* MOSI */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "dram"), /* CKE */
++ SUNXI_FUNCTION(0x3, "pwm0"), /* PWM0 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* IN */
++ SUNXI_FUNCTION(0x5, "uart1"), /* RX */
++ SUNXI_FUNCTION(0x6, "spi1")), /* CLK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "dram"), /* DDR_REF_D */
++ SUNXI_FUNCTION(0x3, "ir0"), /* RX */
++ SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
++ SUNXI_FUNCTION(0x5, "uart1"), /* TX */
++ SUNXI_FUNCTION(0x6, "spi1")), /* MISO */
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
++ SUNXI_FUNCTION(0x3, "mmc1")), /* CLK */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "spi0"), /* CS */
++ SUNXI_FUNCTION(0x3, "mmc1")), /* CMD */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
++ SUNXI_FUNCTION(0x3, "mmc1")), /* D0 */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
++ SUNXI_FUNCTION(0x3, "uart0")), /* TX */
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D2 */
++ SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
++ SUNXI_FUNCTION(0x4, "rsb"), /* SDA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D3 */
++ SUNXI_FUNCTION(0x3, "uart1"), /* RTS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D4*/
++ SUNXI_FUNCTION(0x3, "uart1"), /* CTS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D5 */
++ SUNXI_FUNCTION(0x3, "uart1"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D6 */
++ SUNXI_FUNCTION(0x3, "uart1"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D7 */
++ SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D10 */
++ SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D11 */
++ SUNXI_FUNCTION(0x3, "i2s"), /* MCLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D12 */
++ SUNXI_FUNCTION(0x3, "i2s"), /* BCLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D13 */
++ SUNXI_FUNCTION(0x3, "i2s"), /* LRCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D14 */
++ SUNXI_FUNCTION(0x3, "i2s"), /* IN */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D15 */
++ SUNXI_FUNCTION(0x3, "i2s"), /* OUT */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D18 */
++ SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
++ SUNXI_FUNCTION(0x4, "rsb"), /* SCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D19 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D20 */
++ SUNXI_FUNCTION(0x3, "lvds1"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D21 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
++ SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D22 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
++ SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* D23 */
++ SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* CLK */
++ SUNXI_FUNCTION(0x3, "spi0"), /* CS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* DE */
++ SUNXI_FUNCTION(0x3, "spi0"), /* MOSI */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* HYSNC */
++ SUNXI_FUNCTION(0x3, "spi0"), /* CLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */
++ SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)),
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
++ SUNXI_FUNCTION(0x3, "lcd"), /* D0 */
++ SUNXI_FUNCTION(0x4, "i2c2"), /* SCK */
++ SUNXI_FUNCTION(0x5, "uart0"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
++ SUNXI_FUNCTION(0x3, "lcd"), /* D1 */
++ SUNXI_FUNCTION(0x4, "i2c2"), /* SDA */
++ SUNXI_FUNCTION(0x5, "uart0"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
++ SUNXI_FUNCTION(0x3, "lcd"), /* D8 */
++ SUNXI_FUNCTION(0x4, "clk"), /* OUT */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D0 */
++ SUNXI_FUNCTION(0x3, "lcd"), /* D9 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* BCLK */
++ SUNXI_FUNCTION(0x5, "rsb"), /* SCK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D1 */
++ SUNXI_FUNCTION(0x3, "lcd"), /* D16 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* LRCK */
++ SUNXI_FUNCTION(0x5, "rsb"), /* SDA */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D2 */
++ SUNXI_FUNCTION(0x3, "lcd"), /* D17 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* IN */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D3 */
++ SUNXI_FUNCTION(0x3, "pwm1"), /* PWM1 */
++ SUNXI_FUNCTION(0x4, "i2s"), /* OUT */
++ SUNXI_FUNCTION(0x5, "spdif"), /* OUT */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D4 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* TX */
++ SUNXI_FUNCTION(0x4, "spi1"), /* CS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D5 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* RX */
++ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D6 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
++ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "csi"), /* D7 */
++ SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
++ SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "clk0"), /* OUT */
++ SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */
++ SUNXI_FUNCTION(0x4, "ir"), /* RX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
++ SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */
++ SUNXI_FUNCTION(0x4, "pwm0"), /* PWM0 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
++
++ /* Hole */
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
++ SUNXI_FUNCTION(0x3, "jtag"), /* MS */
++ SUNXI_FUNCTION(0x4, "ir0"), /* MS */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
++ SUNXI_FUNCTION(0x3, "dgb0"), /* DI */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
++ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
++ SUNXI_FUNCTION(0x3, "jtag"), /* DO */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
++ SUNXI_FUNCTION(0x3, "uart0"), /* TX */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
++ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
++ SUNXI_FUNCTION(0x0, "gpio_in"),
++ SUNXI_FUNCTION(0x1, "gpio_out"),
++ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
++ SUNXI_FUNCTION(0x3, "jtag"), /* CK */
++ SUNXI_FUNCTION(0x4, "pwm1"), /* PWM1 */
++ SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
++};
++
++static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {
++ .pins = suniv_f1c100s_pins,
++ .npins = ARRAY_SIZE(suniv_f1c100s_pins),
++ .irq_banks = 3,
++ .disable_strict_mode = true,
++};
++
++static int suniv_pinctrl_probe(struct platform_device *pdev)
++{
++ return sunxi_pinctrl_init(pdev,
++ &suniv_f1c100s_pinctrl_data);
++}
++
++static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {
++ { .compatible = "allwinner,suniv-f1c100s-pinctrl", },
++ {}
++};
++
++static struct platform_driver suniv_f1c100s_pinctrl_driver = {
++ .probe = suniv_pinctrl_probe,
++ .driver = {
++ .name = "suniv-f1c100s-pinctrl",
++ .of_match_table = suniv_f1c100s_pinctrl_match,
++ },
++};
++builtin_platform_driver(suniv_f1c100s_pinctrl_driver);
+
+From patchwork Wed Nov 21 18:30:43 2018
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+ Wed, 21 Nov 2018 10:32:00 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 10/17] dt-bindings: clock: Add Allwinner suniv F1C100s
+ CCU
+Date: Wed, 21 Nov 2018 21:30:43 +0300
+Message-Id:
+ <88a177299386b610d429d4c1eb2566727aef7b17.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-clk.vger.kernel.org>
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+
+Add compatiple string for Allwinner suniv F1C100s CCU.
+Add clock and reset definitions.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ .../devicetree/bindings/clock/sunxi-ccu.txt | 1 +
+ include/dt-bindings/clock/suniv-ccu-f1c100s.h | 69 ++++++++++++++++++++++
+ include/dt-bindings/reset/suniv-ccu-f1c100s.h | 37 ++++++++++++
+ 3 files changed, 107 insertions(+)
+ create mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h
+ create mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h
+
+diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+index 47d2e90..e3bd88a 100644
+--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
++++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+@@ -22,6 +22,7 @@ Required properties :
+ - "allwinner,sun50i-h5-ccu"
+ - "allwinner,sun50i-h6-ccu"
+ - "allwinner,sun50i-h6-r-ccu"
++ - "allwinner,suniv-f1c100s-ccu"
+ - "nextthing,gr8-ccu"
+
+ - reg: Must contain the registers base address and length
+diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
+new file mode 100644
+index 0000000..56f6d0d
+--- /dev/null
++++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
+@@ -0,0 +1,69 @@
++/*
++ * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++ */
++
++#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
++#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
++
++#define CLK_CPU 11
++
++#define CLK_BUS_MMC0 14
++#define CLK_BUS_MMC1 15
++#define CLK_BUS_DRAM 16
++#define CLK_BUS_SPI0 17
++#define CLK_BUS_SPI1 18
++#define CLK_BUS_OTG 19
++#define CLK_BUS_VE 20
++#define CLK_BUS_LCD 21
++#define CLK_BUS_DEINTERLACE 22
++#define CLK_BUS_CSI 23
++#define CLK_BUS_TVD 24
++#define CLK_BUS_TVE 25
++#define CLK_BUS_DE_BE 26
++#define CLK_BUS_DE_FE 27
++#define CLK_BUS_CODEC 28
++#define CLK_BUS_SPDIF 29
++#define CLK_BUS_IR 30
++#define CLK_BUS_RSB 31
++#define CLK_BUS_I2S0 32
++#define CLK_BUS_I2C0 33
++#define CLK_BUS_I2C1 34
++#define CLK_BUS_I2C2 35
++#define CLK_BUS_PIO 36
++#define CLK_BUS_UART0 37
++#define CLK_BUS_UART1 38
++#define CLK_BUS_UART2 39
++
++#define CLK_MMC0 40
++#define CLK_MMC0_SAMPLE 41
++#define CLK_MMC0_OUTPUT 42
++#define CLK_MMC1 43
++#define CLK_MMC1_SAMPLE 44
++#define CLK_MMC1_OUTPUT 45
++#define CLK_I2S 46
++#define CLK_SPDIF 47
++
++#define CLK_USB_PHY0 48
++
++#define CLK_DRAM_VE 49
++#define CLK_DRAM_CSI 50
++#define CLK_DRAM_DEINTERLACE 51
++#define CLK_DRAM_TVD 52
++#define CLK_DRAM_DE_FE 53
++#define CLK_DRAM_DE_BE 54
++
++#define CLK_DE_BE 55
++#define CLK_DE_FE 56
++#define CLK_TCON 57
++#define CLK_DEINTERLACE 58
++#define CLK_TVE2_CLK 59
++#define CLK_TVE1_CLK 60
++#define CLK_TVD 61
++#define CLK_CSI 62
++#define CLK_VE 63
++#define CLK_CODEC 64
++#define CLK_AVS 65
++
++#endif
+diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
+new file mode 100644
+index 0000000..95f1ed0
+--- /dev/null
++++ b/include/dt-bindings/reset/suniv-ccu-f1c100s.h
+@@ -0,0 +1,37 @@
++/*
++ * Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.xyz>
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++ */
++
++#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_
++#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_
++
++#define RST_USB_PHY0 0
++#define RST_BUS_MMC0 1
++#define RST_BUS_MMC1 2
++#define RST_BUS_DRAM 3
++#define RST_BUS_SPI0 4
++#define RST_BUS_SPI1 5
++#define RST_BUS_OTG 6
++#define RST_BUS_VE 7
++#define RST_BUS_LCD 8
++#define RST_BUS_DEINTERLACE 9
++#define RST_BUS_CSI 10
++#define RST_BUS_TVD 11
++#define RST_BUS_TVE 12
++#define RST_BUS_DE_BE 13
++#define RST_BUS_DE_FE 14
++#define RST_BUS_CODEC 15
++#define RST_BUS_SPDIF 16
++#define RST_BUS_IR 17
++#define RST_BUS_RSB 18
++#define RST_BUS_I2S0 19
++#define RST_BUS_I2C0 20
++#define RST_BUS_I2C1 21
++#define RST_BUS_I2C2 22
++#define RST_BUS_UART0 23
++#define RST_BUS_UART1 24
++#define RST_BUS_UART2 25
++
++#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */
+
+From patchwork Wed Nov 21 18:30:44 2018
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+ Wed, 21 Nov 2018 10:32:02 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 11/17] clk: sunxi-ng: add support for suniv F1C100s SoC
+Date: Wed, 21 Nov 2018 21:30:44 +0300
+Message-Id:
+ <07f02fdac83c27d208aba1c6537d051df651778e.1542824904.git.mesihkilinc@gmail.com>
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+
+The suniv F1C100s SoC (the chip in some new F-series products of
+Allwinner)
+has a CCU which seems to be a stripped version of the CCU in SoCs after
+sun6i.
+
+Add support for the CCU.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ drivers/clk/sunxi-ng/Kconfig | 5 +
+ drivers/clk/sunxi-ng/Makefile | 1 +
+ drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 536 +++++++++++++++++++++++++++++++
+ drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 34 ++
+ 4 files changed, 576 insertions(+)
+ create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+ create mode 100644 drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
+
+diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
+index 826674d..429ea4a 100644
+--- a/drivers/clk/sunxi-ng/Kconfig
++++ b/drivers/clk/sunxi-ng/Kconfig
+@@ -6,6 +6,11 @@ config SUNXI_CCU
+
+ if SUNXI_CCU
+
++config SUNIV_F1C100S_CCU
++ bool "Support for the Allwinner newer F1C100s CCU"
++ default MACH_SUNIV
++ depends on MACH_SUNIV || COMPILE_TEST
++
+ config SUN50I_A64_CCU
+ bool "Support for the Allwinner A64 CCU"
+ default ARM64 && ARCH_SUNXI
+diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
+index 4945470..4c7bee8 100644
+--- a/drivers/clk/sunxi-ng/Makefile
++++ b/drivers/clk/sunxi-ng/Makefile
+@@ -21,6 +21,7 @@ obj-y += ccu_nm.o
+ obj-y += ccu_mp.o
+
+ # SoC support
++obj-$(CONFIG_SUNIV_F1C100S_CCU) += ccu-suniv-f1c100s.o
+ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
+ obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
+ obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
+diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+new file mode 100644
+index 0000000..d933dba
+--- /dev/null
++++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+@@ -0,0 +1,536 @@
++/*
++ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.io>
++ *
++ * SPDX-License-Identifier: GPL-2.0
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of_address.h>
++
++#include "ccu_common.h"
++#include "ccu_reset.h"
++
++#include "ccu_div.h"
++#include "ccu_gate.h"
++#include "ccu_mp.h"
++#include "ccu_mult.h"
++#include "ccu_nk.h"
++#include "ccu_nkm.h"
++#include "ccu_nkmp.h"
++#include "ccu_nm.h"
++#include "ccu_phase.h"
++
++#include "ccu-suniv-f1c100s.h"
++
++static struct ccu_nkmp pll_cpu_clk = {
++ .enable = BIT(31),
++ .lock = BIT(28),
++
++ .n = _SUNXI_CCU_MULT(8, 5),
++ .k = _SUNXI_CCU_MULT(4, 2),
++ .m = _SUNXI_CCU_DIV(0, 2),
++ /* MAX is guessed by the BSP table */
++ .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
++
++ .common = {
++ .reg = 0x000,
++ .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
++ &ccu_nkmp_ops,
++ CLK_SET_RATE_UNGATE),
++ },
++};
++
++/*
++ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
++ * the base (2x, 4x and 8x), and one variable divider (the one true
++ * pll audio).
++ *
++ * We don't have any need for the variable divider for now, so we just
++ * hardcode it to match with the clock names
++ */
++#define SUNIV_PLL_AUDIO_REG 0x008
++
++static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
++ "osc24M", 0x008,
++ 8, 7, /* N */
++ 0, 5, /* M */
++ BIT(31), /* gate */
++ BIT(28), /* lock */
++ CLK_SET_RATE_UNGATE);
++
++static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
++ "osc24M", 0x010,
++ 8, 7, /* N */
++ 0, 4, /* M */
++ BIT(24), /* frac enable */
++ BIT(25), /* frac select */
++ 270000000, /* frac rate 0 */
++ 297000000, /* frac rate 1 */
++ BIT(31), /* gate */
++ BIT(28), /* lock */
++ CLK_SET_RATE_UNGATE);
++
++static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
++ "osc24M", 0x018,
++ 8, 7, /* N */
++ 0, 4, /* M */
++ BIT(24), /* frac enable */
++ BIT(25), /* frac select */
++ 270000000, /* frac rate 0 */
++ 297000000, /* frac rate 1 */
++ BIT(31), /* gate */
++ BIT(28), /* lock */
++ CLK_SET_RATE_UNGATE);
++
++static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr",
++ "osc24M", 0x020,
++ 8, 5, /* N */
++ 4, 2, /* K */
++ 0, 2, /* M */
++ BIT(31), /* gate */
++ BIT(28), /* lock */
++ CLK_IS_CRITICAL);
++
++static struct ccu_nk pll_periph_clk = {
++ .enable = BIT(31),
++ .lock = BIT(28),
++ .k = _SUNXI_CCU_MULT(4, 2),
++ .n = _SUNXI_CCU_MULT(8, 5),
++ .common = {
++ .reg = 0x028,
++ .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
++ &ccu_nk_ops, 0),
++ },
++};
++
++static const char * const cpu_parents[] = { "osc32k", "osc24M",
++ "pll-cpu", "pll-cpu" };
++static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
++ 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
++
++static const char * const ahb_parents[] = { "osc32k", "osc24M",
++ "cpu", "pll-periph" };
++static const struct ccu_mux_var_prediv ahb_predivs[] = {
++ { .index = 3, .shift = 6, .width = 2 },
++};
++static struct ccu_div ahb_clk = {
++ .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
++
++ .mux = {
++ .shift = 12,
++ .width = 2,
++
++ .var_predivs = ahb_predivs,
++ .n_var_predivs = ARRAY_SIZE(ahb_predivs),
++ },
++
++ .common = {
++ .reg = 0x054,
++ .features = CCU_FEATURE_VARIABLE_PREDIV,
++ .hw.init = CLK_HW_INIT_PARENTS("ahb",
++ ahb_parents,
++ &ccu_div_ops,
++ 0),
++ },
++};
++
++static struct clk_div_table apb_div_table[] = {
++ { .val = 0, .div = 2 },
++ { .val = 1, .div = 2 },
++ { .val = 2, .div = 4 },
++ { .val = 3, .div = 8 },
++ { /* Sentinel */ },
++};
++static SUNXI_CCU_DIV_TABLE(apb_clk, "apb", "ahb",
++ 0x054, 8, 2, apb_div_table, 0);
++
++static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb",
++ 0x060, BIT(8), 0);
++static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb",
++ 0x060, BIT(9), 0);
++static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb",
++ 0x060, BIT(14), 0);
++static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb",
++ 0x060, BIT(20), 0);
++static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb",
++ 0x060, BIT(21), 0);
++static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb",
++ 0x060, BIT(24), 0);
++
++static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb",
++ 0x064, BIT(0), 0);
++static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb",
++ 0x064, BIT(4), 0);
++static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb",
++ 0x064, BIT(5), 0);
++static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb",
++ 0x064, BIT(8), 0);
++static SUNXI_CCU_GATE(bus_tvd_clk, "bus-tvd", "ahb",
++ 0x064, BIT(9), 0);
++static SUNXI_CCU_GATE(bus_tve_clk, "bus-tve", "ahb",
++ 0x064, BIT(10), 0);
++static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb",
++ 0x064, BIT(12), 0);
++static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb",
++ 0x064, BIT(14), 0);
++
++static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb",
++ 0x068, BIT(0), 0);
++static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb",
++ 0x068, BIT(1), 0);
++static SUNXI_CCU_GATE(bus_ir_clk, "bus-ir", "apb",
++ 0x068, BIT(2), 0);
++static SUNXI_CCU_GATE(bus_rsb_clk, "bus-rsb", "apb",
++ 0x068, BIT(3), 0);
++static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb",
++ 0x068, BIT(12), 0);
++static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb",
++ 0x068, BIT(16), 0);
++static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb",
++ 0x068, BIT(17), 0);
++static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb",
++ 0x068, BIT(18), 0);
++static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb",
++ 0x068, BIT(19), 0);
++static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb",
++ 0x068, BIT(20), 0);
++static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb",
++ 0x068, BIT(21), 0);
++static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb",
++ 0x068, BIT(22), 0);
++
++static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
++static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
++ 0, 4, /* M */
++ 16, 2, /* P */
++ 24, 2, /* mux */
++ BIT(31), /* gate */
++ 0);
++
++static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
++ 0x088, 20, 3, 0);
++static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
++ 0x088, 8, 3, 0);
++
++static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
++ 0, 4, /* M */
++ 16, 2, /* P */
++ 24, 2, /* mux */
++ BIT(31), /* gate */
++ 0);
++
++static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
++ 0x08c, 20, 3, 0);
++static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
++ 0x08c, 8, 3, 0);
++
++static const char * const i2s_spdif_parents[] = { "pll-audio-8x",
++ "pll-audio-4x",
++ "pll-audio-2x",
++ "pll-audio" };
++
++static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_spdif_parents,
++ 0x0b0, 16, 2, BIT(31), 0);
++
++static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
++ 0x0b4, 16, 2, BIT(31), 0);
++
++/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
++
++static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
++ 0x0cc, BIT(8), 0);
++
++static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
++ 0x100, BIT(0), 0);
++static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
++ 0x100, BIT(1), 0);
++static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace",
++ "pll-ddr", 0x100, BIT(2), 0);
++static SUNXI_CCU_GATE(dram_tvd_clk, "dram-tvd", "pll-ddr",
++ 0x100, BIT(3), 0);
++static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
++ 0x100, BIT(24), 0);
++static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
++ 0x100, BIT(26), 0);
++
++static const char * const de_parents[] = { "pll-video", "pll-periph" };
++static const u8 de_table[] = { 0, 2, };
++static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
++ de_parents, de_table,
++ 0x104, 0, 4, 24, 3, BIT(31), 0);
++
++static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
++ de_parents, de_table,
++ 0x10c, 0, 4, 24, 3, BIT(31), 0);
++
++static const char * const tcon_parents[] = { "pll-video", "pll-video-2x" };
++static const u8 tcon_table[] = { 0, 2, };
++static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon_clk, "tcon",
++ tcon_parents, tcon_table,
++ 0x118, 24, 3, BIT(31),
++ CLK_SET_RATE_PARENT);
++
++static const char * const deinterlace_parents[] = { "pll-video",
++ "pll-video-2x" };
++static const u8 deinterlace_table[] = { 0, 2, };
++static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(deinterlace_clk, "deinterlace",
++ deinterlace_parents, deinterlace_table,
++ 0x11c, 0, 4, 24, 3, BIT(31), 0);
++
++static const char * const tve_clk2_parents[] = { "pll-video",
++ "pll-video-2x" };
++static const u8 tve_clk2_table[] = { 0, 2, };
++static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(tve_clk2_clk, "tve-clk2",
++ tve_clk2_parents, tve_clk2_table,
++ 0x120, 0, 4, 24, 3, BIT(31), 0);
++static SUNXI_CCU_M_WITH_GATE(tve_clk1_clk, "tve-clk1", "tve-clk2",
++ 0x120, 8, 1, BIT(15), 0);
++
++static const char * const tvd_parents[] = { "pll-video", "osc24M",
++ "pll-video-2x" };
++static SUNXI_CCU_M_WITH_MUX_GATE(tvd_clk, "tvd", tvd_parents,
++ 0x124, 0, 4, 24, 3, BIT(31), 0);
++
++static const char * const csi_parents[] = { "pll-video", "osc24M" };
++static const u8 csi_table[] = { 0, 5, };
++static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", csi_parents, csi_table,
++ 0x120, 0, 4, 8, 3, BIT(15), 0);
++
++/*
++ * TODO: BSP says the parent is pll-audio, however common sense and experience
++ * told us it should be pll-ve. pll-ve is totally not used in BSP code.
++ */
++static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
++
++static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
++
++static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
++
++static struct ccu_common *suniv_ccu_clks[] = {
++ &pll_cpu_clk.common,
++ &pll_audio_base_clk.common,
++ &pll_video_clk.common,
++ &pll_ve_clk.common,
++ &pll_ddr0_clk.common,
++ &pll_periph_clk.common,
++ &cpu_clk.common,
++ &ahb_clk.common,
++ &apb_clk.common,
++ &bus_mmc0_clk.common,
++ &bus_mmc1_clk.common,
++ &bus_dram_clk.common,
++ &bus_spi0_clk.common,
++ &bus_spi1_clk.common,
++ &bus_otg_clk.common,
++ &bus_ve_clk.common,
++ &bus_lcd_clk.common,
++ &bus_deinterlace_clk.common,
++ &bus_csi_clk.common,
++ &bus_tve_clk.common,
++ &bus_tvd_clk.common,
++ &bus_de_be_clk.common,
++ &bus_de_fe_clk.common,
++ &bus_codec_clk.common,
++ &bus_spdif_clk.common,
++ &bus_ir_clk.common,
++ &bus_rsb_clk.common,
++ &bus_i2s0_clk.common,
++ &bus_i2c0_clk.common,
++ &bus_i2c1_clk.common,
++ &bus_i2c2_clk.common,
++ &bus_pio_clk.common,
++ &bus_uart0_clk.common,
++ &bus_uart1_clk.common,
++ &bus_uart2_clk.common,
++ &mmc0_clk.common,
++ &mmc0_sample_clk.common,
++ &mmc0_output_clk.common,
++ &mmc1_clk.common,
++ &mmc1_sample_clk.common,
++ &mmc1_output_clk.common,
++ &i2s_clk.common,
++ &spdif_clk.common,
++ &usb_phy0_clk.common,
++ &dram_ve_clk.common,
++ &dram_csi_clk.common,
++ &dram_deinterlace_clk.common,
++ &dram_tvd_clk.common,
++ &dram_de_fe_clk.common,
++ &dram_de_be_clk.common,
++ &de_be_clk.common,
++ &de_fe_clk.common,
++ &tcon_clk.common,
++ &deinterlace_clk.common,
++ &tve_clk2_clk.common,
++ &tve_clk1_clk.common,
++ &tvd_clk.common,
++ &csi_clk.common,
++ &ve_clk.common,
++ &codec_clk.common,
++ &avs_clk.common,
++};
++
++static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
++ "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
++static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
++ "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
++static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
++ "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
++static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
++ "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
++static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x",
++ "pll-video", 1, 2, 0);
++
++static struct clk_hw_onecell_data suniv_hw_clks = {
++ .hws = {
++ [CLK_PLL_CPU] = &pll_cpu_clk.common.hw,
++ [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
++ [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
++ [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
++ [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
++ [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
++ [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
++ [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
++ [CLK_PLL_VE] = &pll_ve_clk.common.hw,
++ [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
++ [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
++ [CLK_CPU] = &cpu_clk.common.hw,
++ [CLK_AHB] = &ahb_clk.common.hw,
++ [CLK_APB] = &apb_clk.common.hw,
++ [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
++ [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
++ [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
++ [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
++ [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
++ [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
++ [CLK_BUS_VE] = &bus_ve_clk.common.hw,
++ [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
++ [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
++ [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
++ [CLK_BUS_TVD] = &bus_tvd_clk.common.hw,
++ [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
++ [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
++ [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
++ [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
++ [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
++ [CLK_BUS_IR] = &bus_ir_clk.common.hw,
++ [CLK_BUS_RSB] = &bus_rsb_clk.common.hw,
++ [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
++ [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
++ [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
++ [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
++ [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
++ [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
++ [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
++ [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
++ [CLK_MMC0] = &mmc0_clk.common.hw,
++ [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
++ [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
++ [CLK_MMC1] = &mmc1_clk.common.hw,
++ [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
++ [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
++ [CLK_I2S] = &i2s_clk.common.hw,
++ [CLK_SPDIF] = &spdif_clk.common.hw,
++ [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
++ [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
++ [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
++ [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
++ [CLK_DRAM_TVD] = &dram_tvd_clk.common.hw,
++ [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
++ [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
++ [CLK_DE_BE] = &de_be_clk.common.hw,
++ [CLK_DE_FE] = &de_fe_clk.common.hw,
++ [CLK_TCON] = &tcon_clk.common.hw,
++ [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
++ [CLK_TVE2_CLK] = &tve_clk2_clk.common.hw,
++ [CLK_TVE1_CLK] = &tve_clk1_clk.common.hw,
++ [CLK_TVD] = &tvd_clk.common.hw,
++ [CLK_CSI] = &csi_clk.common.hw,
++ [CLK_VE] = &ve_clk.common.hw,
++ [CLK_CODEC] = &codec_clk.common.hw,
++ [CLK_AVS] = &avs_clk.common.hw,
++ },
++ .num = CLK_NUMBER,
++};
++
++static struct ccu_reset_map suniv_ccu_resets[] = {
++ [RST_USB_PHY0] = { 0x0cc, BIT(0) },
++
++ [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
++ [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
++ [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
++ [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
++ [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
++ [RST_BUS_OTG] = { 0x2c0, BIT(24) },
++ [RST_BUS_VE] = { 0x2c4, BIT(0) },
++ [RST_BUS_LCD] = { 0x2c4, BIT(4) },
++ [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
++ [RST_BUS_CSI] = { 0x2c4, BIT(8) },
++ [RST_BUS_TVD] = { 0x2c4, BIT(9) },
++ [RST_BUS_TVE] = { 0x2c4, BIT(10) },
++ [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
++ [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
++ [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
++ [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
++ [RST_BUS_IR] = { 0x2d0, BIT(2) },
++ [RST_BUS_RSB] = { 0x2d0, BIT(3) },
++ [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
++ [RST_BUS_I2C0] = { 0x2d0, BIT(16) },
++ [RST_BUS_I2C1] = { 0x2d0, BIT(17) },
++ [RST_BUS_I2C2] = { 0x2d0, BIT(18) },
++ [RST_BUS_UART0] = { 0x2d0, BIT(20) },
++ [RST_BUS_UART1] = { 0x2d0, BIT(21) },
++ [RST_BUS_UART2] = { 0x2d0, BIT(22) },
++};
++
++static const struct sunxi_ccu_desc suniv_ccu_desc = {
++ .ccu_clks = suniv_ccu_clks,
++ .num_ccu_clks = ARRAY_SIZE(suniv_ccu_clks),
++
++ .hw_clks = &suniv_hw_clks,
++
++ .resets = suniv_ccu_resets,
++ .num_resets = ARRAY_SIZE(suniv_ccu_resets),
++};
++
++static struct ccu_pll_nb suniv_pll_cpu_nb = {
++ .common = &pll_cpu_clk.common,
++ /* copy from pll_cpu_clk */
++ .enable = BIT(31),
++ .lock = BIT(28),
++};
++
++static struct ccu_mux_nb suniv_cpu_nb = {
++ .common = &cpu_clk.common,
++ .cm = &cpu_clk.mux,
++ .delay_us = 1, /* > 8 clock cycles at 24 MHz */
++ .bypass_index = 1, /* index of 24 MHz oscillator */
++};
++
++static void __init suniv_f1c100s_ccu_setup(struct device_node *node)
++{
++ void __iomem *reg;
++ u32 val;
++
++ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
++ if (IS_ERR(reg)) {
++ pr_err("%pOF: Could not map the clock registers\n", node);
++ return;
++ }
++
++ /* Force the PLL-Audio-1x divider to 4 */
++ val = readl(reg + SUNIV_PLL_AUDIO_REG);
++ val &= ~GENMASK(19, 16);
++ writel(val | (3 << 16), reg + SUNIV_PLL_AUDIO_REG);
++
++ sunxi_ccu_probe(node, reg, &suniv_ccu_desc);
++
++ /* Gate then ungate PLL CPU after any rate changes */
++ ccu_pll_notifier_register(&suniv_pll_cpu_nb);
++
++ /* Reparent CPU during PLL CPU rate changes */
++ ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
++ &suniv_cpu_nb);
++}
++CLK_OF_DECLARE(suniv_f1c100s_ccu, "allwinner,suniv-f1c100s-ccu",
++ suniv_f1c100s_ccu_setup);
+diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
+new file mode 100644
+index 0000000..1da687a
+--- /dev/null
++++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
+@@ -0,0 +1,34 @@
++/*
++ * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#ifndef _CCU_SUNIV_F1C100S_H_
++#define _CCU_SUNIV_F1C100S_H_
++
++#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
++#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
++
++#define CLK_PLL_CPU 0
++#define CLK_PLL_AUDIO_BASE 1
++#define CLK_PLL_AUDIO 2
++#define CLK_PLL_AUDIO_2X 3
++#define CLK_PLL_AUDIO_4X 4
++#define CLK_PLL_AUDIO_8X 5
++#define CLK_PLL_VIDEO 6
++#define CLK_PLL_VIDEO_2X 7
++#define CLK_PLL_VE 8
++#define CLK_PLL_DDR0 9
++#define CLK_PLL_PERIPH 10
++
++/* CPU clock is exported */
++
++#define CLK_AHB 12
++#define CLK_APB 13
++
++/* All bus gates, DRAM gates and mod clocks are exported */
++
++#define CLK_NUMBER (CLK_AVS + 1)
++
++#endif /* _CCU_SUNIV_F1C100S_H_ */
+
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+ Wed, 21 Nov 2018 10:32:06 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 13/17] SoC: sunxi: Add support for Allwinner ARMv5
+ F1C100s sram
+Date: Wed, 21 Nov 2018 21:30:46 +0300
+Message-Id:
+ <89f6179c17a98f160301fdeef27df35b359847e3.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-clk.vger.kernel.org>
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+
+Allwinner ARMv5 F1C100s has similar sram controller to sun4i A10
+Add compatible strings for it.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ drivers/soc/sunxi/sunxi_sram.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
+index b4b0f34..27f0607 100644
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -99,6 +99,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = {
+ .compatible = "allwinner,sun50i-a64-sram-c",
+ .data = &sun50i_a64_sram_c.data,
+ },
++ {
++ .compatible = "allwinner,suniv-f1c100s-sram-d",
++ .data = &sun4i_a10_sram_d.data,
++ },
+ {}
+ };
+
+@@ -389,6 +393,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = {
+ .compatible = "allwinner,sun50i-a64-system-control",
+ .data = &sun50i_a64_sramc_variant,
+ },
++ {
++ .compatible = "allwinner,suniv-f1c100s-system-control",
++ .data = &sun4i_a10_sramc_variant,
++ },
+ { },
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
+
+From patchwork Wed Nov 21 18:30:47 2018
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+ Wed, 21 Nov 2018 10:32:08 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 14/17] dt-bindings: watchdog: Add Allwinner ARMv5
+ F1C100s wdt
+Date: Wed, 21 Nov 2018 21:30:47 +0300
+Message-Id:
+ <713a56409ba6afb4896d3ac9617f1784c7889f0f.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
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+List-ID: <linux-clk.vger.kernel.org>
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+
+Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31.
+Add definition for it.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
+---
+ Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+index ed11ce0..5eefc56 100644
+--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
++++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+@@ -6,6 +6,7 @@ Required properties:
+ "allwinner,sun4i-a10-wdt"
+ "allwinner,sun6i-a31-wdt"
+ "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt"
++ "allwinner,suniv-f1c100s-wdt"
+ - reg : Specifies base physical address and size of the registers.
+
+ Optional properties:
+
+From patchwork Wed Nov 21 18:30:48 2018
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+ Wed, 21 Nov 2018 10:32:10 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 15/17] watchdog: Add support for Allwinner ARMv5
+ F1C100s wdt
+Date: Wed, 21 Nov 2018 21:30:48 +0300
+Message-Id:
+ <09c57147e53dda00eaae83178d0a25fe3f50dd1e.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
+In-Reply-To: <cover.1542824904.git.mesihkilinc@gmail.com>
+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
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+
+Allwinner ARMv5 F1C100s has similar watchdog timer to sun6i A31.
+Add compatible string for it.
+
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+---
+ drivers/watchdog/sunxi_wdt.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c
+index c6c7365..bc70742 100644
+--- a/drivers/watchdog/sunxi_wdt.c
++++ b/drivers/watchdog/sunxi_wdt.c
+@@ -227,6 +227,7 @@ static const struct sunxi_wdt_reg sun6i_wdt_reg = {
+ static const struct of_device_id sunxi_wdt_dt_ids[] = {
+ { .compatible = "allwinner,sun4i-a10-wdt", .data = &sun4i_wdt_reg },
+ { .compatible = "allwinner,sun6i-a31-wdt", .data = &sun6i_wdt_reg },
++ { .compatible = "allwinner,suniv-f1c100s-wdt", .data = &sun6i_wdt_reg },
+ { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids);
+
+From patchwork Wed Nov 21 18:30:49 2018
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+ Wed, 21 Nov 2018 10:32:12 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>,
+ Mesih Kilinc <mesihkilnc@gmail.com>
+Subject: [RFC PATCH v3 16/17] ARM: dts: suniv: add initial DTSI file for
+ F1C100s
+Date: Wed, 21 Nov 2018 21:30:49 +0300
+Message-Id:
+ <05dab577154c72117678c2f49ae85a9663a630e2.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
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+Sender: linux-clk-owner@vger.kernel.org
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+
+F1C100s is one product with the suniv die, which has a 32MiB co-packaged
+DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a
+initial DTSI for it.
+
+Signed-off-by: Mesih Kilinc <mesihkilnc@gmail.com>
+---
+ arch/arm/boot/dts/suniv-f1c100s.dtsi | 151 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 151 insertions(+)
+ create mode 100644 arch/arm/boot/dts/suniv-f1c100s.dtsi
+
+diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
+new file mode 100644
+index 0000000..3ad64ee
+--- /dev/null
++++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
+@@ -0,0 +1,151 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR X11)
++/*
++ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
++ * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
++ */
++
++#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
++#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
++
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ interrupt-parent = <&intc>;
++
++ clocks {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ osc24M: clk-24M {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <24000000>;
++ clock-output-names = "osc24M";
++ };
++
++ osc32k: clk-32k {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++ clock-frequency = <32768>;
++ clock-output-names = "osc32k";
++ };
++ };
++
++ cpus {
++ #address-cells = <0>;
++ #size-cells = <0>;
++
++ cpu {
++ compatible = "arm,arm926ej-s";
++ device_type = "cpu";
++ };
++ };
++
++ soc {
++ compatible = "simple-bus";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ sram-controller@1c00000 {
++ compatible = "allwinner,suniv-f1c100s-system-control";
++ reg = <0x01c00000 0x30>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ sram_d: sram@10000 {
++ compatible = "mmio-sram";
++ reg = <0x00010000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges = <0 0x00010000 0x1000>;
++
++ otg_sram: sram-section@0 {
++ compatible = "allwinner,suniv-f1c100s-sram-d";
++ reg = <0x0000 0x1000>;
++ status = "disabled";
++ };
++ };
++ };
++
++ ccu: clock@1c20000 {
++ compatible = "allwinner,suniv-f1c100s-ccu";
++ reg = <0x01c20000 0x400>;
++ clocks = <&osc24M>, <&osc32k>;
++ clock-names = "hosc", "losc";
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
++
++ intc: interrupt-controller@1c20400 {
++ compatible = "allwinner,suniv-f1c100s-ic";
++ reg = <0x01c20400 0x400>;
++ interrupt-controller;
++ #interrupt-cells = <1>;
++ };
++
++ pio: pinctrl@1c20800 {
++ compatible = "allwinner,suniv-f1c100s-pinctrl";
++ reg = <0x01c20800 0x400>;
++ interrupts = <38>, <39>, <40>;
++ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
++ clock-names = "apb", "hosc", "losc";
++ gpio-controller;
++ interrupt-controller;
++ #interrupt-cells = <3>;
++ #gpio-cells = <3>;
++
++ uart0_pins_a: uart-pins-pe {
++ pins = "PE0", "PE1";
++ function = "uart0";
++ };
++ };
++
++ timer@1c20c00 {
++ compatible = "allwinner,suniv-f1c100s-timer";
++ reg = <0x01c20c00 0x90>;
++ interrupts = <13>;
++ clocks = <&osc24M>;
++ };
++
++ wdt: watchdog@1c20ca0 {
++ compatible = "allwinner,suniv-f1c100s-wdt";
++ reg = <0x01c20ca0 0x20>;
++ };
++
++ uart0: serial@1c25000 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c25000 0x400>;
++ interrupts = <1>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&ccu CLK_BUS_UART0>;
++ resets = <&ccu RST_BUS_UART0>;
++ status = "disabled";
++ };
++
++ uart1: serial@1c25400 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c25400 0x400>;
++ interrupts = <2>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&ccu CLK_BUS_UART1>;
++ resets = <&ccu RST_BUS_UART1>;
++ status = "disabled";
++ };
++
++ uart2: serial@1c25800 {
++ compatible = "snps,dw-apb-uart";
++ reg = <0x01c25800 0x400>;
++ interrupts = <3>;
++ reg-shift = <2>;
++ reg-io-width = <4>;
++ clocks = <&ccu CLK_BUS_UART2>;
++ resets = <&ccu RST_BUS_UART2>;
++ status = "disabled";
++ };
++ };
++};
+
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+ Wed, 21 Nov 2018 10:32:14 -0800 (PST)
+From: Mesih Kilinc <mesihkilinc@gmail.com>
+To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
+ linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
+ linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
+Cc: Mesih Kilinc <mesihkilinc@gmail.com>,
+ Maxime Ripard <maxime.ripard@free-electrons.com>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Russell King <linux@armlinux.org.uk>,
+ Daniel Lezcano <daniel.lezcano@linaro.org>,
+ Marc Zyngier <marc.zyngier@arm.com>,
+ Linus Walleij <linus.walleij@linaro.org>,
+ Icenowy Zheng <icenowy@aosc.io>,
+ Rob Herring <robh+dt@kernel.org>,
+ Julian Calaby <julian.calaby@gmail.com>
+Subject: [RFC PATCH v3 17/17] ARM: suniv: f1c100s: add device tree for Lichee
+ Pi Nano
+Date: Wed, 21 Nov 2018 21:30:50 +0300
+Message-Id:
+ <055b2e09b14ff1699f2ed8fc879a6e9cfa9c5270.1542824904.git.mesihkilinc@gmail.com>
+X-Mailer: git-send-email 2.7.4
+In-Reply-To: <cover.1542824904.git.mesihkilinc@gmail.com>
+References: <cover.1542824904.git.mesihkilinc@gmail.com>
+Sender: linux-clk-owner@vger.kernel.org
+Precedence: bulk
+List-ID: <linux-clk.vger.kernel.org>
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+
+Lichee Pi Nano is a F1C100s board by Lichee Pi.
+
+Add initial device tree for it.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
+---
+ arch/arm/boot/dts/Makefile | 2 ++
+ arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 26 +++++++++++++++++++++++
+ 2 files changed, 28 insertions(+)
+ create mode 100644 arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index b0e966d..2b96a5b 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -1066,6 +1066,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ dtb-$(CONFIG_MACH_SUN9I) += \
+ sun9i-a80-optimus.dtb \
+ sun9i-a80-cubieboard4.dtb
++dtb-$(CONFIG_MACH_SUNIV) += \
++ suniv-f1c100s-licheepi-nano.dtb
+ dtb-$(CONFIG_ARCH_TANGO) += \
+ tango4-vantage-1172.dtb
+ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
+diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+new file mode 100644
+index 0000000..6ae5ccc
+--- /dev/null
++++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+@@ -0,0 +1,26 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR X11)
++/*
++ * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++/dts-v1/;
++#include "suniv-f1c100s.dtsi"
++
++/ {
++ model = "Lichee Pi Nano";
++ compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
++
++ aliases {
++ serial0 = &uart0;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins_a>;
++ status = "okay";
++};
projects / openwrt / staging / wigyori.git / commitdiff