drm/i915/icl: Calculate link clock using the new registers

Start using the new registers for ICL and on.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180522002558.29262-13-paulo.r.zanoni@intel.com

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 3f042c505430dd03df9735c24c26296398e962f8..b344e0fe08fd5c949bf945e951cf2eb9254307cd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1345,8 +1345,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
        uint32_t cfgcr0, cfgcr1;
        uint32_t p0, p1, p2, dco_freq, ref_clock;
 
-       cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
-       cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+       if (INTEL_GEN(dev_priv) >= 11) {
+               cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id));
+               cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id));
+       } else {
+               cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id));
+               cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id));
+       }
 
        p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
        p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK;