drm/amdgpu/atomfirmware: add parser for gfx_info table
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 20 Mar 2018 17:24:03 +0000 (12:24 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 17 May 2018 15:13:22 +0000 (10:13 -0500)
Add support for the gfx_info table on boards that use atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h

index a0f48cb9b8f06465c9a407e425c5881443ca804b..7014d5875d5ba28edd58a9f4d4526b33d4f4ac51 100644 (file)
@@ -322,3 +322,49 @@ int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 
        return ret;
 }
+
+union gfx_info {
+       struct  atom_gfx_info_v2_4 v24;
+};
+
+int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
+{
+       struct amdgpu_mode_info *mode_info = &adev->mode_info;
+       int index;
+       uint8_t frev, crev;
+       uint16_t data_offset;
+
+       index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                           gfx_info);
+       if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
+                                  &frev, &crev, &data_offset)) {
+               union gfx_info *gfx_info = (union gfx_info *)
+                       (mode_info->atom_context->bios + data_offset);
+               switch (crev) {
+               case 4:
+                       adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se;
+                       adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh;
+                       adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se;
+                       adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se;
+                       adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs;
+                       adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
+                       adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
+                       adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
+                       adev->gfx.config.gs_prim_buffer_depth =
+                               le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
+                       adev->gfx.config.double_offchip_lds_buf =
+                               gfx_info->v24.gc_double_offchip_lds_buffer;
+                       adev->gfx.cu_info.wave_front_size = gfx_info->v24.gc_wave_size;
+                       adev->gfx.cu_info.max_waves_per_simd =
+                               le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
+                       adev->gfx.cu_info.max_scratch_slots_per_cu =
+                               gfx_info->v24.gc_max_scratch_slots_per_cu;
+                       adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
+                       return 0;
+               default:
+                       return -EINVAL;
+               }
+
+       }
+       return -EINVAL;
+}
index 7689c961c4ef62826dce6209ab653c1815e5c70c..20f158fd3b7630db7ddb4d0f5016bd893441dd76 100644 (file)
@@ -30,5 +30,6 @@ int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev);
 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev);
+int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev);
 
 #endif