drm/nouveau/pci: Handle 5-bit and 8-bit tag field

If the hardware supports extended tag field (8-bit ones), then enable it.

This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).

In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.

Fixes: fdo#86537
v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it
v4:
  * Rename `add` argument of nvkm_pci_mask to `value`
  * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
    checks
v5:
  * Rebase code on latest PCI structure
  * Restore PCIe check
  * Fix namings in nvkm_pci_mask
  * Rephrase part of the commit message

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
index 39ca88f36df9e6ced644552a8373007e994dcf12..fee0a97c44c5b8e1384f7427816405e31fe4855e 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h
@@ -24,6 +24,7 @@ struct nvkm_pci {
 u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr);
 void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data);
 void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data);
+u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 value);
 void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow);
 
 int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **);

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
index 21106223c2c37bed8a52bb5a79ddbb77a44ab7fb..d671dcfaff3ce38cf2d951f7bda24f3019c79f30 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c
@@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data)
        pci->func->wr32(pci, addr, data);
 }
 
+u32
+nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 value)
+{
+       u32 data = pci->func->rd32(pci, addr);
+       pci->func->wr32(pci, addr, (data & ~mask) | value);
+       return data;
+}
+
 void
 nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow)
 {

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c
index 8f3b00199d14345d03379a3bb5d9eace668fc2b8..3faa6bfb895bedf1d949ae1ac7ea5c52cfc39e46 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c
@@ -25,8 +25,32 @@
 
 #include <core/pci.h>
 
+void
+g84_pci_init(struct nvkm_pci *pci)
+{
+       /* The following only concerns PCIe cards. */
+       if (!pci_is_pcie(pci->pdev))
+               return;
+
+       /* Tag field is 8-bit long, regardless of EXT_TAG.
+        * However, if EXT_TAG is disabled, only the lower 5 bits of the tag
+        * field should be used, limiting the number of request to 32.
+        *
+        * Apparently, 0x041c stores some limit on the number of requests
+        * possible, so if EXT_TAG is disabled, limit that requests number to
+        * 32
+        *
+        * Fixes fdo#86537
+        */
+       if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
+               nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
+       else
+               nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
+}
+
 static const struct nvkm_pci_func
 g84_pci_func = {
+       .init = g84_pci_init,
        .rd32 = nv40_pci_rd32,
        .wr08 = nv40_pci_wr08,
        .wr32 = nv40_pci_wr32,

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c
index 1714421c25340a7818823bdce297945e0b86b192..cd311ee311cc41679fdb614fdb4e3d44b7b70c8b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c
@@ -25,6 +25,7 @@
 
 static const struct nvkm_pci_func
 g94_pci_func = {
+       .init = g84_pci_init,
        .rd32 = nv40_pci_rd32,
        .wr08 = nv40_pci_wr08,
        .wr32 = nv40_pci_wr32,

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c
index 86f8226532d3adacc326a22311f3ba5e5d2e49e2..25e1ae70867f3d19fb84864cee30d07ab15a0c17 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c
@@ -31,6 +31,7 @@ gf100_pci_msi_rearm(struct nvkm_pci *pci)
 
 static const struct nvkm_pci_func
 gf100_pci_func = {
+       .init = g84_pci_init,
        .rd32 = nv40_pci_rd32,
        .wr08 = nv40_pci_wr08,
        .wr32 = nv40_pci_wr32,

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h
index 1acd4bc64d7e0813a0a151a9a62e75b46631223e..cf46d38d0b0a3b96f97ae392dfdb804af502852a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h
@@ -20,4 +20,6 @@ void nv40_pci_wr32(struct nvkm_pci *, u16, u32);
 void nv40_pci_msi_rearm(struct nvkm_pci *);
 
 void nv46_pci_msi_rearm(struct nvkm_pci *);
+
+void g84_pci_init(struct nvkm_pci *pci);
 #endif