(0x80 << 8) | pci_cache_line_size);
}
+/*
+ * pcibios_init_bridge() initializes cache line and default latency
+ * for pci controllers and pci-pci bridges
+ */
+void __init pcibios_init_bridge(struct pci_dev *dev)
+{
+ unsigned short bridge_ctl, bridge_ctl_new;
+
+ /* We deal only with pci controllers and pci-pci bridges. */
+ if (!dev || (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
+ return;
+
+ /* PCI-PCI bridge - set the cache line and default latency
+ * (32) for primary and secondary buses.
+ */
+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 32);
+
+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bridge_ctl);
+
+ bridge_ctl_new = bridge_ctl | PCI_BRIDGE_CTL_PARITY |
+ PCI_BRIDGE_CTL_SERR | PCI_BRIDGE_CTL_MASTER_ABORT;
+ dev_info(&dev->dev, "Changing bridge control from 0x%08x to 0x%08x\n",
+ bridge_ctl, bridge_ctl_new);
+
+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bridge_ctl_new);
+}
/*
* pcibios align resources() is called every time generic PCI code
** P2PB's only have 2 BARs, no IRQs.
** I'd like to just ignore them for now.
*/
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
+ pcibios_init_bridge(dev);
continue;
+ }
/* null out the ROM resource if there is one (we don't
* care about an expansion rom on parisc, since it
/*
** P2PB's have no IRQs. ignore them.
*/
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
+ pcibios_init_bridge(dev);
continue;
+ }
/* Adjust INTERRUPT_LINE for this dev */
iosapic_fixup_irq(ldev->iosapic_obj, dev);