temp /= MCELSIUS;
if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
- val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift);
- val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift);
+ val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
+ val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
}
val &= ~(EXYNOS_EMUL_DATA_MASK << EXYNOS_EMUL_DATA_SHIFT);
val |= (temp_to_code(data, temp) << EXYNOS_EMUL_DATA_SHIFT) |
* @tmu_intstat: Register containing the interrupt status values.
* @tmu_intclear: Register for clearing the raised interrupt status.
* @emul_con: TMU emulation controller register.
- * @emul_time_shift: shift bits of emulation time.
* @tmu_irqstatus: register to find which TMU generated interrupts.
* @tmu_pmin: register to get/set the Pmin value.
*/
u32 tmu_intclear;
u32 emul_con;
- u32 emul_time_shift;
u32 tmu_irqstatus;
u32 tmu_pmin;
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
.emul_con = EXYNOS_EMUL_CON,
- .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
};
#define EXYNOS3250_TMU_DATA \
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
.emul_con = EXYNOS_EMUL_CON,
- .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
};
#define EXYNOS4412_TMU_DATA \
.tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
.tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
.emul_con = EXYNOS5260_EMUL_CON,
- .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
};
#define __EXYNOS5260_TMU_DATA \
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
.emul_con = EXYNOS_EMUL_CON,
- .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
};
#define __EXYNOS5420_TMU_DATA \