crypto: inside-secure - set tx_max_cmd_queue to 32

The ORO bridge (connected to the EIP197 write channel) does not
generate back pressure towards the EIP197 when its internal FIFO is
full. It assumes that the EIP will not drive more write transactions
than the maximal supported outstanding (32).

Hence tx_max_cmd_queue must be configured to 5 (or less).

Signed-off-by: Ofer Heifetz <oferh@marvell.com>
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/inside-secure/safexcel.c b/drivers/crypto/inside-secure/safexcel.c
index 5feb83c6238b889c464eee9fdec6ceb0018f777c..9e5d2bf232eb2bd550d5678b7b043485561d3e43 100644 (file)
--- a/drivers/crypto/inside-secure/safexcel.c
+++ b/drivers/crypto/inside-secure/safexcel.c
@@ -306,6 +306,10 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
        else if (((version >> 16) & 0xffff) == EIP197_HIA_VERSION_LE)
                val |= (EIP197_MST_CTRL_NO_BYTE_SWAP >> 24);
 
+       /* For EIP197 set maximum number of TX commands to 2^5 = 32 */
+       if (priv->version == EIP197B || priv->version == EIP197D)
+               val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
+
        writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
 
        /* Configure wr/rd cache values */

diff --git a/drivers/crypto/inside-secure/safexcel.h b/drivers/crypto/inside-secure/safexcel.h
index 94a89664f3d0463d238da213085af35b5c2b855f..95095cb95ba4188a5cba0a6441b627c6efb00036 100644 (file)
--- a/drivers/crypto/inside-secure/safexcel.h
+++ b/drivers/crypto/inside-secure/safexcel.h
@@ -222,6 +222,7 @@
 #define WR_CACHE_4BITS                         (WR_CACHE_3BITS << 1 | BIT(0))
 #define EIP197_MST_CTRL_RD_CACHE(n)            (((n) & 0xf) << 0)
 #define EIP197_MST_CTRL_WD_CACHE(n)            (((n) & 0xf) << 4)
+#define EIP197_MST_CTRL_TX_MAX_CMD(n)          (((n) & 0xf) << 20)
 #define EIP197_MST_CTRL_BYTE_SWAP              BIT(24)
 #define EIP197_MST_CTRL_NO_BYTE_SWAP           BIT(25)