drm/msm: dsi: Provide option to force continuous HS clock

Some DSI peripherals rely on the HS clock on DSI clock lane as their clock
source. If the clock lane transitions between HS and LP states, it
can disrupt the functioning of such peripherals.

The mipi dsi mode flag MIPI_DSI_CLOCK_NON_CONTINUOUS already exists for
such peripheral drivers. Use it to configure the bit CLKLN_HS_FORCE_REQUEST
in DSI_LANE_CTRL.

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 649d20d29f9298a8852e6d0368008becb348fe03..ae061653ca06c037ef4f81a78f5093338417fb0b 100644 (file)
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -787,6 +787,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
                dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
                        DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(LANE_SWAP_0123));
        }
+
+       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
+               dsi_write(msm_host, REG_DSI_LANE_CTRL,
+                       DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+
        data |= DSI_CTRL_ENABLE;
 
        dsi_write(msm_host, REG_DSI_CTRL, data);