drm/amdgpu: drop the bios scratch reg callbacks from nbio
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 8 Dec 2017 18:11:33 +0000 (13:11 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 13 Dec 2017 22:28:07 +0000 (17:28 -0500)
They are not used any longer.  We get the scratch register
locations from the vbios directly now.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu.h
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

index c73eca86c9f11cc55d3330ed3a613e9179a8b417..c31c5496dc5e920b281fb682bfe3cbaa19baa5c7 100644 (file)
@@ -1451,9 +1451,6 @@ struct amdgpu_nbio_funcs {
        u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);
        u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
        u32 (*get_rev_id)(struct amdgpu_device *adev);
-       u32 (*get_atombios_scratch_regs)(struct amdgpu_device *adev, uint32_t idx);
-       void (*set_atombios_scratch_regs)(struct amdgpu_device *adev,
-                                         uint32_t idx, uint32_t val);
        void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
        void (*hdp_flush)(struct amdgpu_device *adev);
        u32 (*get_memsize)(struct amdgpu_device *adev);
index 0d3514808092fa10c239bd9be0a065812c963189..d4da663d5eb0c7aed8826c72302008b757cd8d68 100644 (file)
@@ -43,18 +43,6 @@ static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
        return tmp;
 }
 
-static u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
-                                              uint32_t idx)
-{
-       return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
-}
-
-static void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
-                                               uint32_t idx, uint32_t val)
-{
-       WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
-}
-
 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
        if (enable)
@@ -284,8 +272,6 @@ const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
        .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
        .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
        .get_rev_id = nbio_v6_1_get_rev_id,
-       .get_atombios_scratch_regs = nbio_v6_1_get_atombios_scratch_regs,
-       .set_atombios_scratch_regs = nbio_v6_1_set_atombios_scratch_regs,
        .mc_access_enable = nbio_v6_1_mc_access_enable,
        .hdp_flush = nbio_v6_1_hdp_flush,
        .get_memsize = nbio_v6_1_get_memsize,
index 29d7b4fd7a8828a15465fca64e41fb4b634484fb..17a9131a459846b9a6075d517af548b4c1efd05e 100644 (file)
@@ -44,18 +44,6 @@ static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
        return tmp;
 }
 
-static u32 nbio_v7_0_get_atombios_scratch_regs(struct amdgpu_device *adev,
-                                       uint32_t idx)
-{
-       return RREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx);
-}
-
-static void nbio_v7_0_set_atombios_scratch_regs(struct amdgpu_device *adev,
-                                               uint32_t idx, uint32_t val)
-{
-       WREG32_SOC15_OFFSET(NBIO, 0, mmBIOS_SCRATCH_0, idx, val);
-}
-
 static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
        if (enable)
@@ -279,8 +267,6 @@ const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
        .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
        .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
        .get_rev_id = nbio_v7_0_get_rev_id,
-       .get_atombios_scratch_regs = nbio_v7_0_get_atombios_scratch_regs,
-       .set_atombios_scratch_regs = nbio_v7_0_set_atombios_scratch_regs,
        .mc_access_enable = nbio_v7_0_mc_access_enable,
        .hdp_flush = nbio_v7_0_hdp_flush,
        .get_memsize = nbio_v7_0_get_memsize,