drm/i915/tgl: Add new pll ids

Add 2 new PLLs for additional TC ports. The names for the PLLs on TGL
changed, but most registers remained the same, like MGPLL5_ENABLE,
MGPLL6_ENABLE. So continue to use the name from ICL.

Cc: Madhav Chauhan <madhav.chauhan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-11-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index ed5fae964736eb7dc0b9eba02b55b37eaee1d0ce..e7588799fce565d681a7391b98a37ca3a61e3d78 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -111,11 +111,11 @@ enum intel_dpll_id {
 
 
        /**
-        * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
+        * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
         */
        DPLL_ID_ICL_DPLL0 = 0,
        /**
-        * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
+        * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
         */
        DPLL_ID_ICL_DPLL1 = 1,
        /**
@@ -123,27 +123,40 @@ enum intel_dpll_id {
         */
        DPLL_ID_EHL_DPLL4 = 2,
        /**
-        * @DPLL_ID_ICL_TBTPLL: ICL TBT PLL
+        * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
         */
        DPLL_ID_ICL_TBTPLL = 2,
        /**
-        * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C)
+        * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
+        *                      TGL TC PLL 1 port 1 (TC1)
         */
        DPLL_ID_ICL_MGPLL1 = 3,
        /**
         * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
+        *                      TGL TC PLL 1 port 2 (TC2)
         */
        DPLL_ID_ICL_MGPLL2 = 4,
        /**
         * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
+        *                      TGL TC PLL 1 port 3 (TC3)
         */
        DPLL_ID_ICL_MGPLL3 = 5,
        /**
         * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
+        *                      TGL TC PLL 1 port 4 (TC4)
         */
        DPLL_ID_ICL_MGPLL4 = 6,
+       /**
+        * @DPLL_ID_TGL_TCPLL5: TGL TC PLL port 5 (TC5)
+        */
+       DPLL_ID_TGL_MGPLL5 = 7,
+       /**
+        * @DPLL_ID_TGL_TCPLL6: TGL TC PLL port 6 (TC6)
+        */
+       DPLL_ID_TGL_MGPLL6 = 8,
 };
-#define I915_NUM_PLLS 7
+
+#define I915_NUM_PLLS 9
 
 enum icl_port_dpll_id {
        ICL_PORT_DPLL_DEFAULT,