rtlwifi: correct comment
authorKevin Lo <kevlo@kevlo.org>
Sat, 17 Mar 2018 14:26:07 +0000 (22:26 +0800)
committerKalle Valo <kvalo@codeaurora.org>
Tue, 27 Mar 2018 09:02:17 +0000 (12:02 +0300)
Correct comment.  Set bit 3 and bit 4 of 0x0005 register (REG_APS_FSMCO + 1)
to 0 which means disable WL suspend, not enable WL suspend.

Signed-off-by: Kevin Lo <kevlo@kevlo.org>
Acked-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
drivers/net/wireless/realtek/rtlwifi/rtl8188ee/pwrseq.h
drivers/net/wireless/realtek/rtlwifi/rtl8192ee/pwrseq.h
drivers/net/wireless/realtek/rtlwifi/rtl8723ae/pwrseq.h
drivers/net/wireless/realtek/rtlwifi/rtl8723be/pwrseq.h
drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h

index f2d9c6116e5c7f92f47f9845498bd52683d9975a..8379a3e5198cd77747069af5f38509047d097b80 100644 (file)
        /*wait power state to suspend*/},                               \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0             \
-       /*0x04[12:11] = 2b'01enable WL suspend*/},
+       /*0x04[12:11] = 2b'00 disable WL suspend*/},
 
 #define RTL8188EE_TRANS_CARDEMU_TO_CARDDIS                             \
        {0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        /*wait power state to suspend*/},                               \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0               \
-       /*0x04[12:11] = 2b'01enable WL suspend*/},
+       /*0x04[12:11] = 2b'00 disable WL suspend*/},
 
 #define RTL8188EE_TRANS_CARDEMU_TO_PDN                                 \
        {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
index 781eeaa6af4953f9a9baa19ee4e5ae02c97358f7..c570801508cc9921392e595b29f3a67c1ffd3573 100644 (file)
        /*wait power state to suspend*/                                 \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
         PWR_BASEADDR_SDIO , PWR_CMD_POLLING, BIT(1), BIT(1)},          \
-       /*0x04[12:11] = 2b'01enable WL suspend*/                        \
+       /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
         PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
 
        /*Lock small LDO Register*/                                     \
        {0x00CC, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
         PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(2), 0},                  \
-       /*0x04[12:11] = 2b'01enable WL suspend*/                        \
+       /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
         PWR_BASEADDR_MAC , PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
 
index 4ac7db526f152b70b682b54cdbe46c3304126371..e6c3aac3e9fd1004ac9488517f1227242bc1d193 100644 (file)
  /*wait power state to suspend*/ \
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
                PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)},\
- /*0x04[12:11] = 2b'01enable WL suspend*/ \
+ /*0x04[12:11] = 2b'00 disable WL suspend*/ \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
                PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
 
        {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
                PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO,\
                PWR_CMD_POLLING, BIT(1), BIT(1)},\
- /*0x04[12:11] = 2b'00enable WL suspend*/ \
+ /*0x04[12:11] = 2b'00 disable WL suspend*/ \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
                PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC,\
                PWR_CMD_WRITE, BIT(3)|BIT(4), 0},\
index 0fee5e0e55c29543b6b7ab253f6ad558e717c22e..3367cfbc95021ff90e7e1122f3bf09c5edc44daf 100644 (file)
        /*0x23[4] = 1b'0 12H LDO enter normal mode*/                    \
        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,   \
         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0},                   \
-       /*0x04[12:11] = 2b'01enable WL suspend*/                        \
+       /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
 
        /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/                 \
        {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,    \
         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0},                   \
-       /*0x04[12:11] = 2b'01enable WL suspend*/                        \
+       /*0x04[12:11] = 2b'00 disable WL suspend*/                      \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,    \
         PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},            \
        /*0x23[4] = 1b'0 12H LDO enter normal mode*/                    \
index 36b3e91d996e96c59b91fb9bb759beb36a94d164..6dd575435c63e37ffcdc778ab600d74c55bbb9fe 100644 (file)
@@ -531,7 +531,7 @@ extern struct wlan_pwr_cfg  rtl8812_leave_lps_flow
         /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
-        /*0x04[12:11] = 2b'01enable WL suspend*/},
+        /*0x04[12:11] = 2b'00 disable WL suspend*/},
 
 #define RTL8821A_TRANS_CARDEMU_TO_CARDDIS                              \
        {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
@@ -572,7 +572,7 @@ extern struct wlan_pwr_cfg  rtl8812_leave_lps_flow
         /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/},   \
        {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
-        /*0x04[12:11] = 2b'01enable WL suspend*/},\
+        /*0x04[12:11] = 2b'00 disable WL suspend*/},\
        {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
        PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
         /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \