return true;
}
static void fill_plane_attributes_from_fb(
+ struct amdgpu_device *adev,
struct dc_surface *surface,
const struct amdgpu_framebuffer *amdgpu_fb, bool addReq)
{
memset(&surface->tiling_info, 0, sizeof(surface->tiling_info));
+ /* Fill GFX8 params */
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1)
{
unsigned bankw, bankh, mtaspect, tile_split, num_banks;
}
static void fill_plane_attributes(
+ struct amdgpu_device *adev,
struct dc_surface *surface,
struct drm_plane_state *state, bool addrReq)
{
fill_rects_from_plane_state(state, surface);
fill_plane_attributes_from_fb(
+ crtc->dev->dev_private,
surface,
amdgpu_fb,
addrReq);
}
/* Surface programming */
- fill_plane_attributes(dc_surface, crtc->primary->state, true);
+ fill_plane_attributes(
+ crtc->dev->dev_private,
+ dc_surface,
+ crtc->primary->state,
+ true);
dc_surfaces[0] = dc_surface;
surface = dc_create_surface(dc);
fill_plane_attributes(
+ crtc->dev->dev_private,
surface,
plane_state,
false);