drm/i915/icl: Define Plane Input CSC Coefficient Registers

Defined the plane input csc coefficient registers and macros.
6 registers are used to program a total of 9 coefficients,
added macros to define each of them for all the planes
supporting the feature on pipes. On ICL, bottom 3 planes
have this capability.

v2: Segregated the register macro definition as separate patch
as per Maarten's suggestion.

v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.

v4: No Change

v5: Renamed the register Macro as per Matt's suggestion.

v6: No Change

v7: No Change

v8: No Change

v9: No Change

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1541099420-12419-2-git-send-email-uma.shankar@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 672fcdab4d23303d45b6e1d7372aca64762f6184..158cf4716d03be6ac5333801a14894cfdf7c8de5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6582,6 +6582,7 @@ enum {
 #define _PLANE_COLOR_CTL_3_A                   0x703CC /* GLK+ */
 #define   PLANE_COLOR_PIPE_GAMMA_ENABLE                (1 << 30) /* Pre-ICL */
 #define   PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE     (1 << 28)
+#define   PLANE_COLOR_INPUT_CSC_ENABLE         (1 << 20) /* ICL+ */
 #define   PLANE_COLOR_PIPE_CSC_ENABLE          (1 << 23) /* Pre-ICL */
 #define   PLANE_COLOR_CSC_MODE_BYPASS                  (0 << 17)
 #define   PLANE_COLOR_CSC_MODE_YUV601_TO_RGB709                (1 << 17)
@@ -6598,6 +6599,55 @@ enum {
 #define _PLANE_NV12_BUF_CFG_1_A                0x70278
 #define _PLANE_NV12_BUF_CFG_2_A                0x70378
 
+/* Input CSC Register Definitions */
+#define _PLANE_INPUT_CSC_RY_GY_1_A     0x701E0
+#define _PLANE_INPUT_CSC_RY_GY_2_A     0x702E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1_B     0x711E0
+#define _PLANE_INPUT_CSC_RY_GY_2_B     0x712E0
+
+#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \
+       _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \
+            _PLANE_INPUT_CSC_RY_GY_1_B)
+#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \
+       _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \
+            _PLANE_INPUT_CSC_RY_GY_2_B)
+
+#define PLANE_INPUT_CSC_COEFF(pipe, plane, index)      \
+       _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) +  (index) * 4, \
+                   _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_A         0x701F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_A         0x702F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1_B         0x711F8
+#define _PLANE_INPUT_CSC_PREOFF_HI_2_B         0x712F8
+
+#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe)     \
+       _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \
+            _PLANE_INPUT_CSC_PREOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe)     \
+       _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \
+            _PLANE_INPUT_CSC_PREOFF_HI_2_B)
+#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index)     \
+       _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \
+                   _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4)
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A                0x70204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A                0x70304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B                0x71204
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B                0x71304
+
+#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe)    \
+       _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \
+            _PLANE_INPUT_CSC_POSTOFF_HI_1_B)
+#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe)    \
+       _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \
+            _PLANE_INPUT_CSC_POSTOFF_HI_2_B)
+#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index)    \
+       _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \
+                   _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4)
 
 #define _PLANE_CTL_1_B                         0x71180
 #define _PLANE_CTL_2_B                         0x71280