drm/i915/icl: Calculate DPLL params for DSI

This patch calculates various DPLL dividers and
parameters for DSI encoder and adjust AFE clock
for DSI. For DSI, 8x clock is AFE clock.

v2: Extend haswell_crtc_compute_clock() for Gen11 DSI

v3: Rebase

v4: use port clock instead of bitrate.

v5: Reabse and remove divide by 5

v6 by Jani:
- Fix indent (Madhav)
- Fix dpll state calc for EDP and DP MST

Co-developed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/525d41d0d893dcdc8874d2ce70afa226227ea3f4.1543500285.git.jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e349e2661a1257d2ff264190c4a2afe7cdc7c603..3b4831c2c4b82bcfc6c7dd00e69c195346fd6b87 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9333,10 +9333,12 @@ void hsw_disable_pc8(struct drm_i915_private *dev_priv)
 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
                                      struct intel_crtc_state *crtc_state)
 {
+       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
        struct intel_atomic_state *state =
                to_intel_atomic_state(crtc_state->base.state);
 
-       if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
+       if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) ||
+           IS_ICELAKE(dev_priv)) {
                struct intel_encoder *encoder =
                        intel_get_crtc_new_encoder(state, crtc_state);
 

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 901e15063b24e508eeec6155673e7ecd2ba2e464..d513ca875c67693cf508c389367febdd3ae320d0 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2523,7 +2523,8 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state,
 
        if (intel_port_is_tc(dev_priv, encoder->port))
                ret = icl_calc_tbt_pll(dev_priv, clock, &pll_params);
-       else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+       else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
+                intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
                ret = cnl_ddi_calculate_wrpll(clock, dev_priv, &pll_params);
        else
                ret = icl_calc_dp_combo_pll(dev_priv, clock, &pll_params);