drm/amd/powerplay: implement dpm enable functions of uvd & vce for smu
authorKevin Wang <kevin1.wang@amd.com>
Fri, 25 Jan 2019 07:10:13 +0000 (15:10 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 19 Mar 2019 20:04:00 +0000 (15:04 -0500)
add function of dpm enable uvd & vce for extern module use.

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

index a1faf3f8702ea57268606fdf97abe76a98091ea0..b83981284a7c621f428532dafd731d6d1b6bb999 100644 (file)
@@ -2347,7 +2347,13 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
 
 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+       int ret = 0;
+       if (is_support_sw_smu(adev)) {
+           ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_UVD, enable);
+           if (ret)
+               DRM_ERROR("[SW SMU]: dpm enable uvd failed, state = %s, ret = %d. \n",
+                         enable ? "true" : "false", ret);
+       } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                /* enable/disable UVD */
                mutex_lock(&adev->pm.mutex);
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
@@ -2368,7 +2374,13 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
 
 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
 {
-       if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
+       int ret = 0;
+       if (is_support_sw_smu(adev)) {
+           ret = smu_dpm_set_power_gate(&adev->smu, AMD_IP_BLOCK_TYPE_VCE, enable);
+           if (ret)
+               DRM_ERROR("[SW SMU]: dpm enable vce failed, state = %s, ret = %d. \n",
+                         enable ? "true" : "false", ret);
+       } else if (adev->powerplay.pp_funcs->set_powergating_by_smu) {
                /* enable/disable VCE */
                mutex_lock(&adev->pm.mutex);
                amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
index f4328cf78d221caf730e5af01bdb324c395f37b5..d6578be9219693f0877f1f08f4ef7a7da5395352 100644 (file)
 #include "smu_v11_0.h"
 #include "atom.h"
 
+int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
+                          bool gate)
+{
+       int ret = 0;
+
+       switch (block_type) {
+       case AMD_IP_BLOCK_TYPE_UVD:
+               ret = smu_dpm_set_uvd_enable(smu, gate);
+               break;
+       case AMD_IP_BLOCK_TYPE_VCE:
+               ret = smu_dpm_set_vce_enable(smu, gate);
+               break;
+       default:
+               break;
+       }
+
+       return ret;
+}
+
 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
 {
        /* not support power state */
index 955b3508f1ce7cb25431c1fd62fbae0767a5afb3..53ca9530ed1f770c756e9a904bf0423153ae5d4d 100644 (file)
@@ -698,5 +698,5 @@ extern int smu_display_configuration_change(struct smu_context *smu, const
                                            *display_config);
 extern int smu_get_current_clocks(struct smu_context *smu,
                                  struct amd_pp_clock_info *clocks);
-
+extern int smu_dpm_set_power_gate(struct smu_context *smu,uint32_t block_type, bool gate);
 #endif