MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier

BMIPS5000 and BMIPS5200 processor have no D cache aliases, and this is
properly handled by the per-CPU override added at the end of
r4k_cache_init(), the problem is that the output of probe_pcache()
disagrees with that, since this is too late:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes

With the change moved earlier, we now have a consistent output with the
settings we are intending to have:

Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes.
Primary data cache 32kB, 4-way, VIPT, no aliases, linesize 32 bytes

Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/13011/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 92e54fbdbf9616ef380e7d8665ce4509add34075..226516d9c85183844841b589c194e07bb4d08cc2 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1319,6 +1319,8 @@ static void probe_pcache(void)
 
        case CPU_BMIPS5000:
                c->icache.flags |= MIPS_CACHE_IC_F_DC;
+               /* Cache aliases are handled in hardware; allow HIGHMEM */
+               c->dcache.flags &= ~MIPS_CACHE_ALIASES;
                break;
 
        case CPU_LOONGSON2:
@@ -1758,8 +1760,6 @@ void r4k_cache_init(void)
                flush_icache_range = (void *)b5k_instruction_hazard;
                local_flush_icache_range = (void *)b5k_instruction_hazard;
 
-               /* Cache aliases are handled in hardware; allow HIGHMEM */
-               current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
 
                /* Optimization: an L2 flush implicitly flushes the L1 */
                current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;