arm-trusted-firmware-stm32: bump to v2.12

No need to pass the option no-warn-rwx-segments. Since v2.12, TF-A
automatically selects it if needed.

A patch is added to revert commit 03a581e2 ("feat(stm32mp1-fdts): remove
RTC clock configuration").
This commit removed RTC clock configuration, as it assumed that it was done
correctly by OPTEE.
But it is not the case. Without this patch the RTC is in a bad state,
consequently the wifi module cannot be initialized.

stm32_rtc 5c004000.rtc: rtc_ck is slow
stm32_rtc 5c004000.rtc: Can't enter in init mode. Prescaler config failed.
stm32_rtc: probe of 5c004000.rtc failed with error -110

sdio mmc1:0001:1: Direct firmware load for brcm/brcmfmac43430-sdio.st,stm32mp135f-dk.bin failed with error -2
brcmfmac: brcmf_sdio_htclk: HT Avail timeout (1000000): clkctl 0x50

Tested on STM32MP135F-DK.

Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
Link: https://github.com/openwrt/openwrt/pull/17243
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/package/boot/arm-trusted-firmware-stm32/Makefile b/package/boot/arm-trusted-firmware-stm32/Makefile
index 9d36d39b0c9aa8d1406ea230d8372d2ea9332dcd..7f486885d3ae93cffc1fa511c15036d7dc7bb951 100644 (file)
--- a/package/boot/arm-trusted-firmware-stm32/Makefile
+++ b/package/boot/arm-trusted-firmware-stm32/Makefile
@@ -7,10 +7,13 @@
 
 include $(TOPDIR)/rules.mk
 
-PKG_VERSION:=2.10
+PKG_VERSION:=2.12
 PKG_RELEASE:=1
 
-PKG_HASH:=88215a62291b9ba87da8e50b077741103cdc08fb6c9e1ebd34dfaace746d3201
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL:=https://github.com/ARM-software/arm-trusted-firmware.git
+PKG_SOURCE_VERSION:=v$(PKG_VERSION)
+PKG_MIRROR_HASH:=51b2022baa25df7fd8f2e6d2709c9351c14b17447cda64759a8a1d432f9d1c11
 PKG_MAINTAINER:=Thomas Richard <thomas.richard@bootlin.com>
 
 include $(INCLUDE_DIR)/kernel.mk
@@ -41,7 +44,6 @@ endef
 TFA_TARGETS := stm32mp135f-dk
 
 TFA_MAKE_FLAGS += \
-               $(if $(CONFIG_BINUTILS_VERSION_2_37)$(CONFIG_BINUTILS_VERSION_2_38),,LDFLAGS="-no-warn-rwx-segments") \
                ARCH=aarch32 AARCH32_SP=optee \
                BL32=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-tee-header_v2.bin \
                BL32_EXTRA1=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-tee-pager_v2.bin \

diff --git a/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch b/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch
new file mode 100644 (file)
index 0000000..58b896c
--- /dev/null
+++ b/package/boot/arm-trusted-firmware-stm32/patches/0001-Revert-feat-stm32mp1-fdts-remove-RTC-clock-configura.patch
@@ -0,0 +1,66 @@
+From 0e1a71d84585ec33b479c2cb8c8d65a4f6734dbe Mon Sep 17 00:00:00 2001
+From: Thomas Richard <thomas.richard@bootlin.com>
+Date: Wed, 4 Dec 2024 14:26:52 +0100
+Subject: [PATCH] Revert "feat(stm32mp1-fdts): remove RTC clock configuration"
+
+This reverts commit 703a581e2522bffe21b421c98994dc02aed2934c.
+---
+ fdts/stm32mp135f-dk.dts   | 2 ++
+ fdts/stm32mp157c-ed1.dts  | 2 ++
+ fdts/stm32mp15xx-dkx.dtsi | 2 ++
+ 3 files changed, 6 insertions(+)
+
+--- a/fdts/stm32mp135f-dk.dts
++++ b/fdts/stm32mp135f-dk.dts
+@@ -190,6 +190,7 @@
+               CLK_AXI_PLL2P
+               CLK_MLAHBS_PLL3
+               CLK_CKPER_HSE
++              CLK_RTC_LSE
+               CLK_SDMMC1_PLL4P
+               CLK_SDMMC2_PLL4P
+               CLK_STGEN_HSE
+@@ -211,6 +212,7 @@
+               DIV(DIV_APB4, 1)
+               DIV(DIV_APB5, 2)
+               DIV(DIV_APB6, 1)
++              DIV(DIV_RTC, 0)
+       >;
+ 
+       st,pll_vco {
+--- a/fdts/stm32mp157c-ed1.dts
++++ b/fdts/stm32mp157c-ed1.dts
+@@ -194,6 +194,7 @@
+               CLK_MPU_PLL1P
+               CLK_AXI_PLL2P
+               CLK_MCU_PLL3P
++              CLK_RTC_LSE
+               CLK_MCO1_DISABLED
+               CLK_MCO2_DISABLED
+               CLK_CKPER_HSE
+@@ -242,6 +243,7 @@
+               DIV(DIV_APB3, 1)
+               DIV(DIV_APB4, 1)
+               DIV(DIV_APB5, 2)
++              DIV(DIV_RTC, 23)
+               DIV(DIV_MCO1, 0)
+               DIV(DIV_MCO2, 0)
+       >;
+--- a/fdts/stm32mp15xx-dkx.dtsi
++++ b/fdts/stm32mp15xx-dkx.dtsi
+@@ -198,6 +198,7 @@
+               CLK_MPU_PLL1P
+               CLK_AXI_PLL2P
+               CLK_MCU_PLL3P
++              CLK_RTC_LSE
+               CLK_MCO1_DISABLED
+               CLK_MCO2_DISABLED
+               CLK_CKPER_HSE
+@@ -246,6 +247,7 @@
+               DIV(DIV_APB3, 1)
+               DIV(DIV_APB4, 1)
+               DIV(DIV_APB5, 2)
++              DIV(DIV_RTC, 23)
+               DIV(DIV_MCO1, 0)
+               DIV(DIV_MCO2, 0)
+       >;