net: hns3: some bugfix of ppu(rcb) ras errors

The 3rd and 4th of PPU(RCB) PF Abnormal is RAS errors instead of MSI-X
like other bits. This patch adds process of handling and logging this
two bits. Otherwise, this patch modifies print message of 28th and 29th
bit of PPU MPF Abnormal errors, which keep same with other errors now.

Fixes: f69b10b317f9 ("net: hns3: handle hw errors of PPU(RCB)")
Signed-off-by: Weihang Li <liweihang@hisilicon.com>
Signed-off-by: Peng Li <lipeng321@huawei.com>
Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
index c9c2c850aee4fefd4340c7b5f41e201c330ce57a..4951684cf4d0b55990e971d2430c5c5d584f5513 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
@@ -1038,6 +1038,13 @@ static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
                hclge_log_error(dev, "IGU_EGU_TNL_INT_STS",
                                &hclge_igu_egu_tnl_int[0], status);
 
+       /* log PPU(RCB) errors */
+       desc_data = (__le32 *)&desc[3];
+       status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_RAS_MASK;
+       if (status)
+               hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST0",
+                               &hclge_ppu_pf_abnormal_int[0], status);
+
        /* clear all PF RAS errors */
        hclge_cmd_reuse_desc(&desc[0], false);
        desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
@@ -1373,14 +1380,13 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
                set_bit(HNAE3_GLOBAL_RESET, reset_requests);
        }
 
-       /* log PPU(RCB) errors */
+       /* log PPU(RCB) MPF errors */
        desc_data = (__le32 *)&desc[5];
        status = le32_to_cpu(*(desc_data + 2)) &
                        HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;
        if (status) {
-               dev_warn(dev,
-                        "PPU_MPF_ABNORMAL_INT_ST2[28:29], err_status(0x%x)\n",
-                        status);
+               hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2",
+                               &hclge_ppu_mpf_abnormal_int_st2[0], status);
                set_bit(HNAE3_CORE_RESET, reset_requests);
        }
 
@@ -1427,7 +1433,7 @@ int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
                hclge_log_error(dev, "PPP_PF_ABNORMAL_INT_ST0",
                                &hclge_ppp_pf_abnormal_int[0], status);
 
-       /* PPU(RCB) PF errors */
+       /* log PPU(RCB) PF errors */
        desc_data = (__le32 *)&desc[3];
        status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_MSIX_MASK;
        if (status)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
index 51a7d4eb066a9ba12f501eb351fb2de5f66e10e6..86d6143068c1b0b47bcc114409f1a7498b6d2cce 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h
@@ -79,6 +79,7 @@
 #define HCLGE_PPP_MPF_INT_ST3_MASK     GENMASK(5, 0)
 #define HCLGE_PPU_MPF_INT_ST3_MASK     GENMASK(7, 0)
 #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK        GENMASK(29, 28)
+#define HCLGE_PPU_PF_INT_RAS_MASK      0x18
 #define HCLGE_PPU_PF_INT_MSIX_MASK     0x27
 #define HCLGE_QCN_FIFO_INT_MASK                GENMASK(17, 0)
 #define HCLGE_QCN_ECC_INT_MASK         GENMASK(21, 0)