--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "mt7981.dtsi"
+
+/ {
+ model = "Zbtlink ZBT-Z8103AX";
+ compatible = "zbtlink,zbt-z8103ax", "mediatek,mt7981";
+
+ aliases {
+ serial0 = &uart0;
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_green;
+ label-mac-device = &gmac0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 loglevel=8";
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x10000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ button-mesh {
+ label = "mesh";
+ linux,code = <BTN_0>;
+ linux,input-type = <EV_SW>;
+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ button-reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-wan {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ };
+
+ led-status-blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_green: led-status-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ };
+
+ led_status_red: led-status-red {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 25 GPIO_ACTIVE_LOW>;
+ };
+
+ led-wlan2g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+ function-enumerator = <0>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ led-wlan5g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ function-enumerator = <1>;
+ linux,default-trigger = "phy1tpt";
+ };
+ };
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ /* LAN */
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "2500base-x";
+
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_factory_4 2>;
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ /* WAN */
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_factory_4 3>;
+ };
+};
+
+&mdio_bus {
+ switch: switch@1f {
+ compatible = "mediatek,mt7531";
+ reg = <31>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+ interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "okay";
+
+ spi_nand@0 {
+ compatible = "spi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+
+ spi-max-frequency = <52000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0000000 0x0100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x200000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr_factory_4: macaddr@4 {
+ compatible = "mac-base";
+ reg = <0x4 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@380000 {
+ label = "FIP";
+ reg = <0x380000 0x200000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x4000000>;
+ };
+ };
+ };
+};
+
+&switch {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+
+ conf-pu {
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ status = "okay";
+ nvmem-cells = <&eeprom_factory>;
+ nvmem-cell-names = "eeprom";
+};
projects / openwrt / openwrt.git / commitdiff