drm/i915: Organize plane register writes into tighter bunches

Pull all the plane register writes closer together to avoid having
a lot of unrelated stuff in between them. This will make things more
clear once we'll grab the uncore lock around the entire bunch. Also
in the future we might even consider moving more of the register
value computation out from the plane update hooks. This should make
that easier to do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170309154434.29303-4-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e79166db7ecd89b9a9e4eede10da8c8a4e854517..357dce64706872363c923f132f3a8e34dfc964b5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2984,20 +2984,6 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
        if (INTEL_GEN(dev_priv) < 4) {
                if (intel_crtc->pipe == PIPE_B)
                        dspcntr |= DISPPLANE_SEL_PIPE_B;
-
-               /* pipesrc and dspsize control the size that is scaled from,
-                * which should always be the user's requested size.
-                */
-               I915_WRITE(DSPSIZE(plane),
-                          ((crtc_state->pipe_src_h - 1) << 16) |
-                          (crtc_state->pipe_src_w - 1));
-               I915_WRITE(DSPPOS(plane), 0);
-       } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
-               I915_WRITE(PRIMSIZE(plane),
-                          ((crtc_state->pipe_src_h - 1) << 16) |
-                          (crtc_state->pipe_src_w - 1));
-               I915_WRITE(PRIMPOS(plane), 0);
-               I915_WRITE(PRIMCNSTALPHA(plane), 0);
        }
 
        switch (fb->format->format) {
@@ -3060,6 +3046,22 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
        intel_crtc->adjusted_x = x;
        intel_crtc->adjusted_y = y;
 
+       if (INTEL_GEN(dev_priv) < 4) {
+               /* pipesrc and dspsize control the size that is scaled from,
+                * which should always be the user's requested size.
+                */
+               I915_WRITE(DSPSIZE(plane),
+                          ((crtc_state->pipe_src_h - 1) << 16) |
+                          (crtc_state->pipe_src_w - 1));
+               I915_WRITE(DSPPOS(plane), 0);
+       } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
+               I915_WRITE(PRIMSIZE(plane),
+                          ((crtc_state->pipe_src_h - 1) << 16) |
+                          (crtc_state->pipe_src_w - 1));
+               I915_WRITE(PRIMPOS(plane), 0);
+               I915_WRITE(PRIMCNSTALPHA(plane), 0);
+       }
+
        I915_WRITE(reg, dspcntr);
 
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
@@ -3344,12 +3346,7 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
 
        plane_ctl = PLANE_CTL_ENABLE;
 
-       if (IS_GEMINILAKE(dev_priv)) {
-               I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
-                          PLANE_COLOR_PIPE_GAMMA_ENABLE |
-                          PLANE_COLOR_PIPE_CSC_ENABLE |
-                          PLANE_COLOR_PLANE_GAMMA_DISABLE);
-       } else {
+       if (!IS_GEMINILAKE(dev_priv)) {
                plane_ctl |=
                        PLANE_CTL_PIPE_GAMMA_ENABLE |
                        PLANE_CTL_PIPE_CSC_ENABLE |
@@ -3371,6 +3368,13 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
        intel_crtc->adjusted_x = src_x;
        intel_crtc->adjusted_y = src_y;
 
+       if (IS_GEMINILAKE(dev_priv)) {
+               I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
+                          PLANE_COLOR_PIPE_GAMMA_ENABLE |
+                          PLANE_COLOR_PIPE_CSC_ENABLE |
+                          PLANE_COLOR_PLANE_GAMMA_DISABLE);
+       }
+
        I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
        I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
        I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 300776b9e9354407c3709c7431e7cd44d93424f2..532db7d622902254ec0e2648678043c2d0b03bd3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -233,12 +233,7 @@ skl_update_plane(struct drm_plane *drm_plane,
 
        plane_ctl = PLANE_CTL_ENABLE;
 
-       if (IS_GEMINILAKE(dev_priv)) {
-               I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
-                          PLANE_COLOR_PIPE_GAMMA_ENABLE |
-                          PLANE_COLOR_PIPE_CSC_ENABLE |
-                          PLANE_COLOR_PLANE_GAMMA_DISABLE);
-       } else {
+       if (!IS_GEMINILAKE(dev_priv)) {
                plane_ctl |=
                        PLANE_CTL_PIPE_GAMMA_ENABLE |
                        PLANE_CTL_PIPE_CSC_ENABLE |
@@ -249,12 +244,6 @@ skl_update_plane(struct drm_plane *drm_plane,
        plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
        plane_ctl |= skl_plane_ctl_rotation(rotation);
 
-       if (key->flags) {
-               I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key->min_value);
-               I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key->max_value);
-               I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
-       }
-
        if (key->flags & I915_SET_COLORKEY_DESTINATION)
                plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
        else if (key->flags & I915_SET_COLORKEY_SOURCE)
@@ -266,6 +255,19 @@ skl_update_plane(struct drm_plane *drm_plane,
        crtc_w--;
        crtc_h--;
 
+       if (IS_GEMINILAKE(dev_priv)) {
+               I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
+                          PLANE_COLOR_PIPE_GAMMA_ENABLE |
+                          PLANE_COLOR_PIPE_CSC_ENABLE |
+                          PLANE_COLOR_PLANE_GAMMA_DISABLE);
+       }
+
+       if (key->flags) {
+               I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key->min_value);
+               I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key->max_value);
+               I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
+       }
+
        I915_WRITE(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
        I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
        I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
@@ -433,6 +435,9 @@ vlv_update_plane(struct drm_plane *dplane,
        if (rotation & DRM_REFLECT_X)
                sprctl |= SP_MIRROR;
 
+       if (key->flags & I915_SET_COLORKEY_SOURCE)
+               sprctl |= SP_SOURCE_KEY;
+
        /* Sizes are 0 based */
        src_w--;
        src_h--;
@@ -451,18 +456,14 @@ vlv_update_plane(struct drm_plane *dplane,
 
        linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 
+       if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
+               chv_update_csc(intel_plane, fb->format->format);
+
        if (key->flags) {
                I915_WRITE(SPKEYMINVAL(pipe, plane_id), key->min_value);
                I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key->max_value);
                I915_WRITE(SPKEYMSK(pipe, plane_id), key->channel_mask);
        }
-
-       if (key->flags & I915_SET_COLORKEY_SOURCE)
-               sprctl |= SP_SOURCE_KEY;
-
-       if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
-               chv_update_csc(intel_plane, fb->format->format);
-
        I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
        I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 
@@ -563,6 +564,11 @@ ivb_update_plane(struct drm_plane *plane,
        if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
                sprctl |= SPRITE_PIPE_CSC_ENABLE;
 
+       if (key->flags & I915_SET_COLORKEY_DESTINATION)
+               sprctl |= SPRITE_DEST_KEY;
+       else if (key->flags & I915_SET_COLORKEY_SOURCE)
+               sprctl |= SPRITE_SOURCE_KEY;
+
        /* Sizes are 0 based */
        src_w--;
        src_h--;
@@ -590,11 +596,6 @@ ivb_update_plane(struct drm_plane *plane,
                I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
        }
 
-       if (key->flags & I915_SET_COLORKEY_DESTINATION)
-               sprctl |= SPRITE_DEST_KEY;
-       else if (key->flags & I915_SET_COLORKEY_SOURCE)
-               sprctl |= SPRITE_SOURCE_KEY;
-
        I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
        I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 
@@ -696,6 +697,11 @@ ilk_update_plane(struct drm_plane *plane,
        if (IS_GEN6(dev_priv))
                dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 
+       if (key->flags & I915_SET_COLORKEY_DESTINATION)
+               dvscntr |= DVS_DEST_KEY;
+       else if (key->flags & I915_SET_COLORKEY_SOURCE)
+               dvscntr |= DVS_SOURCE_KEY;
+
        /* Sizes are 0 based */
        src_w--;
        src_h--;
@@ -722,11 +728,6 @@ ilk_update_plane(struct drm_plane *plane,
                I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
        }
 
-       if (key->flags & I915_SET_COLORKEY_DESTINATION)
-               dvscntr |= DVS_DEST_KEY;
-       else if (key->flags & I915_SET_COLORKEY_SOURCE)
-               dvscntr |= DVS_SOURCE_KEY;
-
        I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
        I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);