openrisc: Fix the bitmask for the unit present register

The bits were swapped, as per spec and processor implementation the
power management present bit is 9 and PIC bit is 8. This patch brings
the definitions into spec.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
[shorne@gmail.com: Added commit body]
Signed-off-by: Stafford Horne <shorne@gmail.com>

diff --git a/arch/openrisc/include/asm/spr_defs.h b/arch/openrisc/include/asm/spr_defs.h
index 5dbc668865c48f24825bf4a98bc38b6eab70387c..367dac70326af01731e8d841fa8fd5ce49c36222 100644 (file)
--- a/arch/openrisc/include/asm/spr_defs.h
+++ b/arch/openrisc/include/asm/spr_defs.h
@@ -152,8 +152,8 @@
 #define SPR_UPR_MP        0x00000020  /* MAC present */
 #define SPR_UPR_DUP       0x00000040  /* Debug unit present */
 #define SPR_UPR_PCUP      0x00000080  /* Performance counters unit present */
-#define SPR_UPR_PMP       0x00000100  /* Power management present */
-#define SPR_UPR_PICP      0x00000200  /* PIC present */
+#define SPR_UPR_PICP      0x00000100  /* PIC present */
+#define SPR_UPR_PMP       0x00000200  /* Power management present */
 #define SPR_UPR_TTP       0x00000400  /* Tick timer present */
 #define SPR_UPR_RES       0x00fe0000  /* Reserved */
 #define SPR_UPR_CUP       0xff000000  /* Context units present */