drm/i915: Do not temporarily disable the DPLL on i830

The current code clears the DPLL register entirely when re-enabling
VGA mode temporarily during the DPLL enable sequence. On i830 we want to
keep the DPLLs on all the time, so let's not do this temporary
disabling.

The current code does work, so this doesn't seem super important.
But I prefer that we make the behaviour 100% consistent.

v2: Split this change the DVO 2x clocking patch

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190305192400.23121-1-ville.syrjala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d852cb2820606fbcfdf9704892e6c6514b1a378e..9ee313b42e1e44ee166719b06351923bb27acbb6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1486,8 +1486,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc,
         * the P1/P2 dividers. Otherwise the DPLL will keep using the old
         * dividers, even though the register value does change.
         */
-       I915_WRITE(reg, 0);
-
+       I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS);
        I915_WRITE(reg, dpll);
 
        /* Wait for the clocks to stabilize. */