drm/amd/display: fix DP 422 VID_M half the rate issue.

[Description]
when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N.
for YCbCr420 or compressed YCbCr422, using half rate as  YCbCr444.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
index 1fa2d4fd7a352a2b7525dc4bfc324fd2145ed3d0..67cad0016f9600cb66709f0a760b2d235edb5b06 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
@@ -977,7 +977,7 @@ static void dce110_stream_encoder_dp_unblank(
 
                uint64_t m_vid_l = n_vid;
 
-               m_vid_l *= param->pixel_clk_khz;
+               m_vid_l *= param->timing.pix_clk_100hz / 10;
                m_vid_l = div_u64(m_vid_l,
                        param->link_settings.link_rate
                                * LINK_RATE_REF_FREQ_IN_KHZ);

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 7ec9958ddd2691e73be84274a80a8bb76d901f6b..6b24ddd57a4e480ab2aa6047dc675f7e370b5b31 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1052,9 +1052,8 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
        struct dc_link *link = stream->link;
 
        /* only 3 items below are used by unblank */
-       params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
+       params.timing = pipe_ctx->stream->timing;
        params.link_settings.link_rate = link_settings->link_rate;
-       params.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 
        if (dc_is_dp_signal(pipe_ctx->stream->signal))
                pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 5fcc69c565841e650fc2405e63f23fd35a345b51..eef58536a6ac3981c8075038c48fb680aa72c6e2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2900,6 +2900,29 @@ static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
                tg->funcs->setup_vertical_interrupt2(tg, start_line);
 }
 
+static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
+               struct dc_link_settings *link_settings)
+{
+       struct encoder_unblank_param params = { { 0 } };
+       struct dc_stream_state *stream = pipe_ctx->stream;
+       struct dc_link *link = stream->link;
+
+       /* only 3 items below are used by unblank */
+       params.timing = pipe_ctx->stream->timing;
+
+       params.link_settings.link_rate = link_settings->link_rate;
+
+       if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+               if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+                       params.timing.pix_clk_100hz /= 2;
+               pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
+       }
+
+       if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
+               link->dc->hwss.edp_backlight_control(link, true);
+       }
+}
+
 static const struct hw_sequencer_funcs dcn10_funcs = {
        .program_gamut_remap = program_gamut_remap,
        .init_hw = dcn10_init_hw,
@@ -2921,7 +2944,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
        .update_info_frame = dce110_update_info_frame,
        .enable_stream = dce110_enable_stream,
        .disable_stream = dce110_disable_stream,
-       .unblank_stream = dce110_unblank_stream,
+       .unblank_stream = dcn10_unblank_stream,
        .blank_stream = dce110_blank_stream,
        .enable_audio_stream = dce110_enable_audio_stream,
        .disable_audio_stream = dce110_disable_audio_stream,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index d2a15d2e9561ff26562ab8d1ec5c96e61f52c51f..0d46aa75361b028b07f92fdc745fbf4d7b8ef063 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -836,14 +836,15 @@ void enc1_stream_encoder_dp_unblank(
                uint64_t m_vid_l = n_vid;
 
                /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
-               if (param->pixel_encoding == PIXEL_ENCODING_YCBCR420)
+               if (param->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+                       /*this param->pixel_clk_khz is half of 444 rate for 420 already*/
                        n_multiply = 1;
-
+               }
                /* M / N = Fstream / Flink
                 * m_vid / n_vid = pixel rate / link rate
                 */
 
-               m_vid_l *= param->pixel_clk_khz;
+               m_vid_l *= param->timing.pix_clk_100hz / 10;
                m_vid_l = div_u64(m_vid_l,
                        param->link_settings.link_rate
                                * LINK_RATE_REF_FREQ_IN_KHZ);

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
index 8ba73a47401415dead31ce5608c6439bee062aa5..8aafed8793df899f5c49fa5a433dd54da87db49a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h
@@ -67,8 +67,7 @@ struct encoder_info_frame {
 
 struct encoder_unblank_param {
        struct dc_link_settings link_settings;
-       unsigned int pixel_clk_khz;
-       enum dc_pixel_encoding pixel_encoding;
+       struct dc_crtc_timing timing;
 };
 
 struct encoder_set_dp_phy_pattern_param {