OMAP3: PM: Add D2D clocks and auto-idle setup to PRCM init

Add D2D clocks (modem_fck, sad2d_ick, mad2d_ick) to clock framework
and ensure that auto-idle bits are set for these clocks during PRCM
init.

Also add omap3_d2d_idle() function called durint PRCM setup which
ensures D2D pins are MUX'd correctly to enable retention for
standalone (no-modem) devices.

Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 62021397e5f99e8daa02e2eca649266de3a7f211..9e43fe5209d337b7f149099d469339d670b572e6 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -129,6 +129,9 @@ static struct omap_clk omap34xx_clks[] = {
        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2),
        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2),
        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
+       CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
+       CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
+       CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_343X),
        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_343X),
        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2),

diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 496f0e9caeb26851ae21b2cd0458081303fe9af4..e433aec4efdd2c65587556702df13001c9aaffe6 100644 (file)
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1230,6 +1230,37 @@ static struct clk d2d_26m_fck = {
        .recalc         = &followparent_recalc,
 };
 
+static struct clk modem_fck = {
+       .name           = "modem_fck",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &sys_ck,
+       .init           = &omap2_init_clk_clkdm,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+       .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
+       .clkdm_name     = "d2d_clkdm",
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk sad2d_ick = {
+       .name           = "sad2d_ick",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &l3_ick,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
+       .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
+       .clkdm_name     = "d2d_clkdm",
+       .recalc         = &followparent_recalc,
+};
+
+static struct clk mad2d_ick = {
+       .name           = "mad2d_ick",
+       .ops            = &clkops_omap2_dflt_wait,
+       .parent         = &l3_ick,
+       .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+       .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
+       .clkdm_name     = "d2d_clkdm",
+       .recalc         = &followparent_recalc,
+};
+
 static const struct clksel omap343x_gpt_clksel[] = {
        { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
        { .parent = &sys_ck,       .rates = gpt_sys_rates },
@@ -1947,8 +1978,6 @@ static struct clk usb_l4_ick = {
        .recalc         = &omap2_clksel_recalc,
 };
 
-/* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
-
 /* SECURITY_L4_ICK2 based clocks */
 
 static struct clk security_l4_ick2 = {

diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6f3f5a36aae664960e037d59200dba8fe025feab..6923deb98a2884e1c870514581515a30bd670687 100644 (file)
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -145,6 +145,8 @@
 #define OMAP3430_CLKACTIVITY_MPU_MASK                  (1 << 0)
 
 /* CM_FCLKEN1_CORE specific bits */
+#define OMAP3430_EN_MODEM                              (1 << 31)
+#define OMAP3430_EN_MODEM_SHIFT                                31
 
 /* CM_ICLKEN1_CORE specific bits */
 #define OMAP3430_EN_ICR                                        (1 << 29)
@@ -161,6 +163,8 @@
 #define OMAP3430_EN_MAILBOXES_SHIFT                    7
 #define OMAP3430_EN_OMAPCTRL                           (1 << 6)
 #define OMAP3430_EN_OMAPCTRL_SHIFT                     6
+#define OMAP3430_EN_SAD2D                              (1 << 3)
+#define OMAP3430_EN_SAD2D_SHIFT                                3
 #define OMAP3430_EN_SDRC                               (1 << 1)
 #define OMAP3430_EN_SDRC_SHIFT                         1
 
@@ -176,6 +180,10 @@
 #define OMAP3430_EN_DES1                               (1 << 0)
 #define OMAP3430_EN_DES1_SHIFT                         0
 
+/* CM_ICLKEN3_CORE */
+#define OMAP3430_EN_MAD2D_SHIFT                                3
+#define OMAP3430_EN_MAD2D                              (1 << 3)
+
 /* CM_FCLKEN3_CORE specific bits */
 #define OMAP3430ES2_EN_TS_SHIFT                                1
 #define OMAP3430ES2_EN_TS_MASK                         (1 << 1)
@@ -231,6 +239,8 @@
 #define OMAP3430ES2_ST_CPEFUSE_MASK                    (1 << 0)
 
 /* CM_AUTOIDLE1_CORE */
+#define OMAP3430_AUTO_MODEM                            (1 << 31)
+#define OMAP3430_AUTO_MODEM_SHIFT                      31
 #define OMAP3430ES2_AUTO_MMC3                          (1 << 30)
 #define OMAP3430ES2_AUTO_MMC3_SHIFT                    30
 #define OMAP3430ES2_AUTO_ICR                           (1 << 29)
@@ -287,6 +297,8 @@
 #define OMAP3430_AUTO_HSOTGUSB_SHIFT                   4
 #define OMAP3430ES1_AUTO_D2D                           (1 << 3)
 #define OMAP3430ES1_AUTO_D2D_SHIFT                     3
+#define OMAP3430_AUTO_SAD2D                            (1 << 3)
+#define OMAP3430_AUTO_SAD2D_SHIFT                      3
 #define OMAP3430_AUTO_SSI                              (1 << 0)
 #define OMAP3430_AUTO_SSI_SHIFT                                0
 
@@ -308,6 +320,8 @@
 #define        OMAP3430ES2_AUTO_USBTLL                         (1 << 2)
 #define OMAP3430ES2_AUTO_USBTLL_SHIFT                  2
 #define OMAP3430ES2_AUTO_USBTLL_MASK                   (1 << 2)
+#define OMAP3430_AUTO_MAD2D_SHIFT                      3
+#define OMAP3430_AUTO_MAD2D                            (1 << 3)
 
 /* CM_CLKSEL_CORE */
 #define OMAP3430_CLKSEL_SSI_SHIFT                      8

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 54876aca2d45aa300c3d6c4e37d13245f32f017c..f72e25465429a8612de9f9d5d07dae7c67c21fc2 100644 (file)
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -415,14 +415,32 @@ static void __init omap3_iva_idle(void)
                          OMAP3430_IVA2_MOD, RM_RSTCTRL);
 }
 
-static void __init prcm_setup_regs(void)
+static void __init omap3_d2d_idle(void)
 {
+       u16 mask, padconf;
+
+       /* In a stand alone OMAP3430 where there is not a stacked
+        * modem for the D2D Idle Ack and D2D MStandby must be pulled
+        * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
+        * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
+       mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
+       padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
+       padconf |= mask;
+       omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
+
+       padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
+       padconf |= mask;
+       omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
+
        /* reset modem */
        prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
                          OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
                          CORE_MOD, RM_RSTCTRL);
        prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
+}
 
+static void __init prcm_setup_regs(void)
+{
        /* XXX Reset all wkdeps. This should be done when initializing
         * powerdomains */
        prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -442,6 +460,7 @@ static void __init prcm_setup_regs(void)
         * Note that in the long run this should be done by clockfw
         */
        cm_write_mod_reg(
+               OMAP3430_AUTO_MODEM |
                OMAP3430ES2_AUTO_MMC3 |
                OMAP3430ES2_AUTO_ICR |
                OMAP3430_AUTO_AES2 |
@@ -469,7 +488,7 @@ static void __init prcm_setup_regs(void)
                OMAP3430_AUTO_OMAPCTRL |
                OMAP3430ES1_AUTO_FSHOSTUSB |
                OMAP3430_AUTO_HSOTGUSB |
-               OMAP3430ES1_AUTO_D2D | /* This is es1 only */
+               OMAP3430_AUTO_SAD2D |
                OMAP3430_AUTO_SSI,
                CORE_MOD, CM_AUTOIDLE1);
 
@@ -483,6 +502,7 @@ static void __init prcm_setup_regs(void)
 
        if (omap_rev() > OMAP3430_REV_ES1_0) {
                cm_write_mod_reg(
+                       OMAP3430_AUTO_MAD2D |
                        OMAP3430ES2_AUTO_USBTLL,
                        CORE_MOD, CM_AUTOIDLE3);
        }
@@ -576,6 +596,7 @@ static void __init prcm_setup_regs(void)
                          OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 
        omap3_iva_idle();
+       omap3_d2d_idle();
 }
 
 static int __init pwrdms_setup(struct powerdomain *pwrdm)

diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index a9f05e5bb2bae8665e6b7a47baadd4dff71635c6..fcc5a9b7697391b3afaa1af9da87e128f4835f6d 100644 (file)
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -144,6 +144,10 @@
 #define OMAP343X_CONTROL_PBIAS_LITE    (OMAP2_CONTROL_GENERAL + 0x02b0)
 #define OMAP343X_CONTROL_TEMP_SENSOR   (OMAP2_CONTROL_GENERAL + 0x02b4)
 
+/* 34xx D2D idle-related pins, handled by PM core */
+#define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
+#define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.