drm/nouveau: allocate fixed amount of PRAMIN per channel on all chipsets

Previously only done on nv50+

This commit also switches unknown NV2x/NV3x chipsets to noaccel mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 7d86e05ac883d7cb943dcb4dc2337bd42d7198b8..b6bcb254f4ab49ab123834d78f4e62e58ac0398a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -229,25 +229,12 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan,
         * available.
         */
        if (chan) {
-               if (chan->ramin_heap.ml_entry.next) {
-                       NV_DEBUG(dev, "private heap\n");
-                       pramin = &chan->ramin_heap;
-               } else
-               if (dev_priv->card_type < NV_50) {
-                       NV_DEBUG(dev, "global heap fallback\n");
-                       pramin = &dev_priv->ramin_heap;
-               }
+               NV_DEBUG(dev, "channel heap\n");
+               pramin = &chan->ramin_heap;
        } else {
                NV_DEBUG(dev, "global heap\n");
                pramin = &dev_priv->ramin_heap;
-       }
-
-       if (!pramin) {
-               NV_ERROR(dev, "No PRAMIN heap!\n");
-               return -EINVAL;
-       }
 
-       if (!chan) {
                ret = engine->instmem.populate(dev, gpuobj, &size);
                if (ret) {
                        nouveau_gpuobj_del(dev, &gpuobj);
@@ -911,6 +898,7 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
        base = 0;
 
        /* PGRAPH context */
+       size += dev_priv->engine.graph.grctx_size;
 
        if (dev_priv->card_type == NV_50) {
                /* Various fixed table thingos */
@@ -921,12 +909,8 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
                size += 0x8000;
                /* RAMFC */
                size += 0x1000;
-               /* PGRAPH context */
-               size += 0x70000;
        }
 
-       NV_DEBUG(dev, "ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n",
-                chan->id, size, base);
        ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0,
                                     &chan->ramin);
        if (ret) {
@@ -959,15 +943,11 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
 
        NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
 
-       /* Reserve a block of PRAMIN for the channel
-        *XXX: maybe on <NV50 too at some point
-        */
-       if (0 || dev_priv->card_type == NV_50) {
-               ret = nouveau_gpuobj_channel_init_pramin(chan);
-               if (ret) {
-                       NV_ERROR(dev, "init pramin\n");
-                       return ret;
-               }
+       /* Allocate a chunk of memory for per-channel object storage */
+       ret = nouveau_gpuobj_channel_init_pramin(chan);
+       if (ret) {
+               NV_ERROR(dev, "init pramin\n");
+               return ret;
        }
 
        /* NV50 VM

diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index f3e6dd70d22ef571a4fb185efc2c29ea8ebacff1..0c776ee81e8542d63b15fa38c34a22d87e63c9c1 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -370,53 +370,42 @@ nv20_graph_create_context(struct nouveau_channel *chan)
 {
        struct drm_device *dev = chan->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
        void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
-       unsigned int ctx_size;
        unsigned int idoffs = 0x28/4;
        int ret;
 
        switch (dev_priv->chipset) {
        case 0x20:
-               ctx_size = NV20_GRCTX_SIZE;
                ctx_init = nv20_graph_context_init;
                idoffs = 0;
                break;
        case 0x25:
        case 0x28:
-               ctx_size = NV25_GRCTX_SIZE;
                ctx_init = nv25_graph_context_init;
                break;
        case 0x2a:
-               ctx_size = NV2A_GRCTX_SIZE;
                ctx_init = nv2a_graph_context_init;
                idoffs = 0;
                break;
        case 0x30:
        case 0x31:
-               ctx_size = NV30_31_GRCTX_SIZE;
                ctx_init = nv30_31_graph_context_init;
                break;
        case 0x34:
-               ctx_size = NV34_GRCTX_SIZE;
                ctx_init = nv34_graph_context_init;
                break;
        case 0x35:
        case 0x36:
-               ctx_size = NV35_36_GRCTX_SIZE;
                ctx_init = nv35_36_graph_context_init;
                break;
        default:
-               ctx_size = 0;
-               ctx_init = nv35_36_graph_context_init;
-               NV_ERROR(dev, "Please contact the devs if you want your NV%x"
-                             " card to work\n", dev_priv->chipset);
-               return -ENOSYS;
-               break;
+               BUG_ON(1);
        }
 
-       ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, ctx_size, 16,
-                                         NVOBJ_FLAG_ZERO_ALLOC,
-                                         &chan->ramin_grctx);
+       ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
+                                    16, NVOBJ_FLAG_ZERO_ALLOC,
+                                    &chan->ramin_grctx);
        if (ret)
                return ret;
 
@@ -535,9 +524,27 @@ nv20_graph_init(struct drm_device *dev)
 {
        struct drm_nouveau_private *dev_priv =
                (struct drm_nouveau_private *)dev->dev_private;
+       struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
        uint32_t tmp, vramsz;
        int ret, i;
 
+       switch (dev_priv->chipset) {
+       case 0x20:
+               pgraph->grctx_size = NV20_GRCTX_SIZE;
+               break;
+       case 0x25:
+       case 0x28:
+               pgraph->grctx_size = NV25_GRCTX_SIZE;
+               break;
+       case 0x2a:
+               pgraph->grctx_size = NV2A_GRCTX_SIZE;
+               break;
+       default:
+               NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
+               pgraph->accel_blocked = true;
+               return 0;
+       }
+
        nv_wr32(dev, NV03_PMC_ENABLE,
                nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
        nv_wr32(dev, NV03_PMC_ENABLE,
@@ -647,8 +654,27 @@ int
 nv30_graph_init(struct drm_device *dev)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
+       struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
        int ret, i;
 
+       switch (dev_priv->chipset) {
+       case 0x30:
+       case 0x31:
+               pgraph->grctx_size = NV30_31_GRCTX_SIZE;
+               break;
+       case 0x34:
+               pgraph->grctx_size = NV34_GRCTX_SIZE;
+               break;
+       case 0x35:
+       case 0x36:
+               pgraph->grctx_size = NV35_36_GRCTX_SIZE;
+               break;
+       default:
+               NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
+               pgraph->accel_blocked = true;
+               return 0;
+       }
+
        nv_wr32(dev, NV03_PMC_ENABLE,
                nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
        nv_wr32(dev, NV03_PMC_ENABLE,