mlxsw: pci: Query free running clock PCI BAR and offsets

Query free running clock PCI BAR and offsets during the pci_init.

Signed-off-by: Shalom Toledo <shalomt@mellanox.com>
Acked-by: Jiri Pirko <jiri@mellanox.com>
Reviewed-by: Petr Machata <petrm@mellanox.com>
Signed-off-by: Ido Schimmel <idosch@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c
index b40455f8293d85487b2bb95ca7c47cec5ae9c4e8..6acb9bbfdf89fd49ba19dede7f8b1774e9c2290e 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/pci.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c
@@ -102,6 +102,7 @@ struct mlxsw_pci_queue_type_group {
 struct mlxsw_pci {
        struct pci_dev *pdev;
        u8 __iomem *hw_addr;
+       u64 free_running_clock_offset;
        struct mlxsw_pci_queue_type_group queues[MLXSW_PCI_QUEUE_TYPE_COUNT];
        u32 doorbell_offset;
        struct mlxsw_core *core;
@@ -1414,6 +1415,15 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
        mlxsw_pci->doorbell_offset =
                mlxsw_cmd_mbox_query_fw_doorbell_page_offset_get(mbox);
 
+       if (mlxsw_cmd_mbox_query_fw_fr_rn_clk_bar_get(mbox) != 0) {
+               dev_err(&pdev->dev, "Unsupported free running clock BAR queried from hw\n");
+               err = -EINVAL;
+               goto err_fr_rn_clk_bar;
+       }
+
+       mlxsw_pci->free_running_clock_offset =
+               mlxsw_cmd_mbox_query_fw_free_running_clock_offset_get(mbox);
+
        num_pages = mlxsw_cmd_mbox_query_fw_fw_pages_get(mbox);
        err = mlxsw_pci_fw_area_init(mlxsw_pci, mbox, num_pages);
        if (err)
@@ -1469,6 +1479,7 @@ err_query_resources:
 err_boardinfo:
        mlxsw_pci_fw_area_fini(mlxsw_pci);
 err_fw_area_init:
+err_fr_rn_clk_bar:
 err_doorbell_page_bar:
 err_iface_rev:
 err_query_fw:
@@ -1672,6 +1683,24 @@ static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
        return err;
 }
 
+static u32 mlxsw_pci_read_frc_h(void *bus_priv)
+{
+       struct mlxsw_pci *mlxsw_pci = bus_priv;
+       u64 frc_offset;
+
+       frc_offset = mlxsw_pci->free_running_clock_offset;
+       return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_H(frc_offset));
+}
+
+static u32 mlxsw_pci_read_frc_l(void *bus_priv)
+{
+       struct mlxsw_pci *mlxsw_pci = bus_priv;
+       u64 frc_offset;
+
+       frc_offset = mlxsw_pci->free_running_clock_offset;
+       return mlxsw_pci_read32(mlxsw_pci, FREE_RUNNING_CLOCK_L(frc_offset));
+}
+
 static const struct mlxsw_bus mlxsw_pci_bus = {
        .kind                   = "pci",
        .init                   = mlxsw_pci_init,
@@ -1679,6 +1708,8 @@ static const struct mlxsw_bus mlxsw_pci_bus = {
        .skb_transmit_busy      = mlxsw_pci_skb_transmit_busy,
        .skb_transmit           = mlxsw_pci_skb_transmit,
        .cmd_exec               = mlxsw_pci_cmd_exec,
+       .read_frc_h             = mlxsw_pci_read_frc_h,
+       .read_frc_l             = mlxsw_pci_read_frc_l,
        .features               = MLXSW_BUS_F_TXRX | MLXSW_BUS_F_RESET,
 };
 
@@ -1740,6 +1771,7 @@ static int mlxsw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
        mlxsw_pci->bus_info.device_kind = driver_name;
        mlxsw_pci->bus_info.device_name = pci_name(mlxsw_pci->pdev);
        mlxsw_pci->bus_info.dev = &pdev->dev;
+       mlxsw_pci->bus_info.read_frc_capable = true;
        mlxsw_pci->id = id;
 
        err = mlxsw_core_bus_device_register(&mlxsw_pci->bus_info,

diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
index 8648ca1712543abf8e6ef7bcabfae895c4009465..e57e42e2d2b24821f39bb1f26b3aec31441af75e 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
@@ -43,6 +43,9 @@
 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)   \
        ((offset) + (type_offset) + (num) * 4)
 
+#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset) (offset)
+#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset) ((offset) + 4)
+
 #define MLXSW_PCI_CQS_MAX      96
 #define MLXSW_PCI_EQS_COUNT    2
 #define MLXSW_PCI_EQ_ASYNC_NUM 0