drm/i915: Renaming CCK related reg definitions

Rename the DISPLAY_TRUNK_* and DISPLAY_FREQUENCY_* bits to CCK_... instead
of DISPLAY_... to make it clear they apply to all CCK clock control registers.
Suggested by Ville.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 59124a5714a97ad70469ab13b74e5a8b4e78294d..aca25bf7c11e8fb292f856340adf844dd93ac3d5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -729,11 +729,11 @@ enum skl_disp_power_wells {
 #define  DSI_PLL_M1_DIV_SHIFT                  0
 #define  DSI_PLL_M1_DIV_MASK                   (0x1ff << 0)
 #define CCK_DISPLAY_CLOCK_CONTROL              0x6b
-#define  DISPLAY_TRUNK_FORCE_ON                        (1 << 17)
-#define  DISPLAY_TRUNK_FORCE_OFF               (1 << 16)
-#define  DISPLAY_FREQUENCY_STATUS              (0x1f << 8)
-#define  DISPLAY_FREQUENCY_STATUS_SHIFT                8
-#define  DISPLAY_FREQUENCY_VALUES              (0x1f << 0)
+#define  CCK_TRUNK_FORCE_ON                    (1 << 17)
+#define  CCK_TRUNK_FORCE_OFF                   (1 << 16)
+#define  CCK_FREQUENCY_STATUS                  (0x1f << 8)
+#define  CCK_FREQUENCY_STATUS_SHIFT            8
+#define  CCK_FREQUENCY_VALUES                  (0x1f << 0)
 
 /**
  * DOC: DPIO

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7f3c482be1f44f01184be4be85ee26ac13a5d69c..36591e372db20b947a40fc19d3d3e4a4d4d0830b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5807,12 +5807,12 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
 
                /* adjust cdclk divider */
                val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
-               val &= ~DISPLAY_FREQUENCY_VALUES;
+               val &= ~CCK_FREQUENCY_VALUES;
                val |= divider;
                vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 
                if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
-                             DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
+                             CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
                             50))
                        DRM_ERROR("timed out waiting for CDclk change\n");
        }
@@ -6733,10 +6733,10 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
        val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
        mutex_unlock(&dev_priv->sb_lock);
 
-       divider = val & DISPLAY_FREQUENCY_VALUES;
+       divider = val & CCK_FREQUENCY_VALUES;
 
-       WARN((val & DISPLAY_FREQUENCY_STATUS) !=
-            (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
+       WARN((val & CCK_FREQUENCY_STATUS) !=
+            (divider << CCK_FREQUENCY_STATUS_SHIFT),
             "cdclk change in progress\n");
 
        return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);