clk: mediatek: fix PWM clock source by adding a fixed-factor clock

The clock for which all PWM devices on MT7623 or MT2701 actually depending
on has to be divided by four from its parent clock axi_sel in the clock
path prior to PWM devices.

Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
clock axi_sel allows that PWM devices can have the correct resolution
calculation.

Cc: stable@vger.kernel.org
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 8e7f16fd87c93b80f586d2f223c95c38a10be967..deca7527f92f6d033175d199b4aead45258aa01c 100644 (file)
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -148,6 +148,7 @@ static const struct mtk_fixed_factor top_fixed_divs[] = {
        FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
        FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
        FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
+       FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
 };
 
 static const char * const axi_parents[] = {
@@ -857,13 +858,13 @@ static const struct mtk_gate peri_clks[] = {
        GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
        GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
        GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
-       GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
-       GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
-       GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
-       GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
-       GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
-       GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
-       GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
+       GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
+       GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
+       GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
+       GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
+       GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
+       GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
+       GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
        GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
        GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),