x86/MCE/AMD, EDAC/mce_amd: Add new error descriptions for some SMCA bank types

Some SMCA bank types on future systems will report new error types even
though the bank type is not treated as a new version. These new error
types will reported by bits that are reserved in past systems.

Add the new error descriptions to the lists in edac_mce_amd.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Shirish S <Shirish.S@amd.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20190201225534.8177-4-Yazen.Ghannam@amd.com

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index bd1331b241cad163acd237c29c19b4ded125a95e..e64de5149e50e8c35518cf56ed4d0ebc61e9c78f 100644 (file)
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -144,22 +144,22 @@ static struct smca_hwid smca_hwid_mcatypes[] = {
        { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0), 0x0 },
 
        /* ZN Core (HWID=0xB0) MCA types */
-       { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFEF },
+       { SMCA_LS,       HWID_MCATYPE(0xB0, 0x0), 0x1FFFFF },
        { SMCA_IF,       HWID_MCATYPE(0xB0, 0x1), 0x3FFF },
        { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2), 0xF },
        { SMCA_DE,       HWID_MCATYPE(0xB0, 0x3), 0x1FF },
        /* HWID 0xB0 MCATYPE 0x4 is Reserved */
-       { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0x7FF },
+       { SMCA_EX,       HWID_MCATYPE(0xB0, 0x5), 0xFFF },
        { SMCA_FP,       HWID_MCATYPE(0xB0, 0x6), 0x7F },
        { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7), 0xFF },
 
        /* Data Fabric MCA types */
        { SMCA_CS,       HWID_MCATYPE(0x2E, 0x0), 0x1FF },
-       { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0xF },
+       { SMCA_PIE,      HWID_MCATYPE(0x2E, 0x1), 0x1F },
        { SMCA_CS_V2,    HWID_MCATYPE(0x2E, 0x2), 0x3FFF },
 
        /* Unified Memory Controller MCA type */
-       { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0x3F },
+       { SMCA_UMC,      HWID_MCATYPE(0x96, 0x0), 0xFF },
 
        /* Parameter Block MCA type */
        { SMCA_PB,       HWID_MCATYPE(0x05, 0x0), 0x1 },

diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index 184c90172d176881a1417e1572b26c1380294a59..c79e650aa6066e97074207fdb107ee3384db4512 100644 (file)
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -155,7 +155,7 @@ static const char * const smca_ls_mce_desc[] = {
        "Store queue parity",
        "Miss address buffer payload parity",
        "L1 TLB parity",
-       "Reserved",
+       "DC Tag error type 5",
        "DC tag error type 6",
        "DC tag error type 1",
        "Internal error type 1",
@@ -222,6 +222,7 @@ static const char * const smca_ex_mce_desc[] = {
        "Retire status queue parity error",
        "Scheduling queue parity error",
        "Branch buffer queue parity error",
+       "Hardware Assertion error",
 };
 
 static const char * const smca_fp_mce_desc[] = {
@@ -279,6 +280,7 @@ static const char * const smca_pie_mce_desc[] = {
        "Internal PIE register security violation",
        "Error on GMI link",
        "Poison data written to internal PIE register",
+       "A deferred error was detected in the DF"
 };
 
 static const char * const smca_umc_mce_desc[] = {
@@ -288,6 +290,8 @@ static const char * const smca_umc_mce_desc[] = {
        "Advanced peripheral bus error",
        "Command/address parity error",
        "Write data CRC error",
+       "DCQ SRAM ECC error",
+       "AES SRAM ECC error",
 };
 
 static const char * const smca_pb_mce_desc[] = {