ARM: zynq: DT: Add missing address for L2 pl310

By in sync with others node and add also baseaddr
to the node name.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 1836a60444facdd120a9a8e614c2724a51bf7e07..772381fe07bb0fd550571c1940ffc5f4cfb882da 100644 (file)
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -136,7 +136,7 @@
                              <0xF8F00100 0x100>;
                };
 
-               L2: cache-controller {
+               L2: cache-controller@f8f02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xF8F02000 0x1000>;
                        arm,data-latency = <3 2 2>;