gpu: host1x: Program stream ID to bypass without SMMU
authorArnd Bergmann <arnd@arndb.de>
Wed, 6 Mar 2019 13:57:43 +0000 (14:57 +0100)
committerThierry Reding <treding@nvidia.com>
Thu, 11 Apr 2019 15:40:35 +0000 (17:40 +0200)
If SMMU support is not available, fall back to programming the bypass
stream ID (0x7f).

Fixes: de5469c21ff9 ("gpu: host1x: Program the channel stream ID")
Suggested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
[treding@nvidia.com: rebase this on top of a later build fix]
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/host1x/hw/channel_hw.c

index 4030d64916f004a03781fc7c5b7a36173bcf344f..0c0eb43abf657f2369872b3f5026b3a965f4a298 100644 (file)
@@ -114,9 +114,13 @@ static inline void synchronize_syncpt_base(struct host1x_job *job)
 
 static void host1x_channel_set_streamid(struct host1x_channel *channel)
 {
-#if IS_ENABLED(CONFIG_IOMMU_API) &&  HOST1X_HW >= 6
+#if HOST1X_HW >= 6
+       u32 sid = 0x7f;
+#ifdef CONFIG_IOMMU_API
        struct iommu_fwspec *spec = dev_iommu_fwspec_get(channel->dev->parent);
-       u32 sid = spec ? spec->ids[0] & 0xffff : 0x7f;
+       if (spec)
+               sid = spec->ids[0] & 0xffff;
+#endif
 
        host1x_ch_writel(channel, sid, HOST1X_CHANNEL_SMMU_STREAMID);
 #endif