drm/amdgpu: limit the number of IVs processed at once

Only process a maximum of 32 IVs before writing back the RPTR. This improves
hw handling when we get close to an overflow in the ring buffer.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 1c50be3ab8a965ff8ba404afa522f241cb28158f..934dfdcb4e73fe0205714ae513007c5aa13ecdf3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -142,6 +142,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
  */
 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
 {
+       unsigned int count = AMDGPU_IH_MAX_NUM_IVS;
        u32 wptr;
 
        if (!ih->enabled || adev->shutdown)
@@ -159,7 +160,7 @@ restart_ih:
        /* Order reading of wptr vs. reading of IH ring data */
        rmb();
 
-       while (ih->rptr != wptr) {
+       while (ih->rptr != wptr && --count) {
                amdgpu_irq_dispatch(adev, ih);
                ih->rptr &= ih->ptr_mask;
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 113a1ba13d4a4b0214e6d76f629e7a7dbc31f4f1..4e0bb645176d7e244267050bbab5f31d068e7dba 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -24,6 +24,9 @@
 #ifndef __AMDGPU_IH_H__
 #define __AMDGPU_IH_H__
 
+/* Maximum number of IVs processed at once */
+#define AMDGPU_IH_MAX_NUM_IVS  32
+
 struct amdgpu_device;
 struct amdgpu_iv_entry;