drm/radeon: fix vm page table block size calculation

The page offset is 12 bits.  For example if we have an
8 GB VM, we'd need 33 bits.  The number of bits needed
for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20
(log2(8) + 17).

Noticed by Alexey during code review.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 6fbab15821128b44bc88d36a14f2e3894df857d7..55065d8442056d5ff5d1a0f5400878035e5d3158 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1126,7 +1126,7 @@ static void radeon_check_arguments(struct radeon_device *rdev)
        if (radeon_vm_block_size == -1) {
 
                /* Total bits covered by PD + PTs */
-               unsigned bits = ilog2(radeon_vm_size) + 17;
+               unsigned bits = ilog2(radeon_vm_size) + 18;
 
                /* Make sure the PD is 4K in size up to 8GB address space.
                   Above that split equal between PD and PTs */