drm/armada: move write to dma_ctrl0 to armada_drm_crtc_plane_disable()

Move the write to clear the DMA enable bit, and augment it with clearing
the graphics enable bit for the primary plane.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index 007fc5d3eb5419f6bc858c2d6ab95ad3acd37926..89decc5bdcd4daebafacfa5ab3e15842d754d5fb 100644 (file)
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -703,7 +703,7 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
        struct drm_plane *plane)
 {
-       u32 sram_para1;
+       u32 sram_para1, dma_ctrl0_mask;
 
        /*
         * Drop our reference on any framebuffer attached to this plane.
@@ -719,9 +719,17 @@ void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc,
        sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66;
 
        /* Power down most RAMs and FIFOs if this is the primary plane */
-       if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+       if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
                sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
                              CFG_PDWN32x32 | CFG_PDWN64x66;
+               dma_ctrl0_mask = CFG_GRA_ENA;
+       } else {
+               dma_ctrl0_mask = CFG_DMA_ENA;
+       }
+
+       spin_lock_irq(&dcrtc->irq_lock);
+       armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0);
+       spin_unlock_irq(&dcrtc->irq_lock);
 
        armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1);
 }

diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c
index 1032f9b3d5f1655d4d2359824e571e1433dd5d02..9686d79335a0434379e0cb92dcaa92cbef187cc1 100644 (file)
--- a/drivers/gpu/drm/armada/armada_overlay.c
+++ b/drivers/gpu/drm/armada/armada_overlay.c
@@ -275,7 +275,6 @@ static int armada_ovl_plane_disable(struct drm_plane *plane)
 
        spin_lock_irq(&dcrtc->irq_lock);
        armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update);
-       armada_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
        dplane->ctrl0 = 0;
        spin_unlock_irq(&dcrtc->irq_lock);