arm64: dts: mt7622: add power domain controller device nodes

add power domain controller nodes

Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
index 73e5d628a8c8e02ac140e056c4c3574c73b6cd2f..81207e652d59d667b0eeed9fb3d13f93f5fd84c2 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/mt7622-clk.h>
+#include <dt-bindings/power/mt7622-power.h>
 #include <dt-bindings/reset/mt7622-reset.h>
 
 / {
@@ -109,6 +110,20 @@
                #reset-cells = <1>;
        };
 
+       scpsys: scpsys@10006000 {
+               compatible = "mediatek,mt7622-scpsys",
+                            "syscon";
+               #power-domain-cells = <1>;
+               reg = <0 0x10006000 0 0x1000>;
+               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+               infracfg = <&infracfg>;
+               clocks = <&topckgen CLK_TOP_HIF_SEL>;
+               clock-names = "hif_sel";
+       };
+
        sysirq: interrupt-controller@10200620 {
                compatible = "mediatek,mt7622-sysirq",
                             "mediatek,mt6577-sysirq";