drm/i915/ringbuffer: EMIT_INVALIDATE *before* switch context
authorChris Wilson <chris@chris-wilson.co.uk>
Fri, 19 Apr 2019 11:17:47 +0000 (12:17 +0100)
committerChris Wilson <chris@chris-wilson.co.uk>
Fri, 26 Apr 2019 10:37:58 +0000 (11:37 +0100)
Despite what I think the prm recommends, commit f2253bd9859b
("drm/i915/ringbuffer: EMIT_INVALIDATE after switch context") turned out
to be a huge mistake when enabling Ironlake contexts as the GPU would
hang on either a MI_FLUSH or PIPE_CONTROL immediately following the
MI_SET_CONTEXT of an active mesa context (more vanilla contexts, e.g.
simple rendercopies with igt, do not suffer).

Ville found the following clue,

  "[DevCTG+]: For the invalidate operation of the pipe control, the
   following pointers are affected. The
   invalidate operation affects the restore of these packets. If the pipe
   control invalidate operation is completed
   before the context save, the indirect pointers will not be restored from
   memory.
   1. Pipeline State Pointer
   2. Media State Pointer
   3. Constant Buffer Packet"

which suggests by us emitting the INVALIDATE prior to the MI_SET_CONTEXT,
we prevent the context-restore from chasing the dangling pointers within
the image, and explains why this likely prevents the GPU hang.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190419111749.3910-1-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/gt/intel_ringbuffer.c

index b791da2711e0af208f03dc3a15b009f803e9ff30..1418ed0c48757e04d3492a923e32fc8270dcca6c 100644 (file)
@@ -1886,12 +1886,12 @@ static int ring_request_alloc(struct i915_request *request)
         */
        request->reserved_space += LEGACY_REQUEST_SIZE;
 
-       ret = switch_context(request);
+       /* Unconditionally invalidate GPU caches and TLBs. */
+       ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
        if (ret)
                return ret;
 
-       /* Unconditionally invalidate GPU caches and TLBs. */
-       ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
+       ret = switch_context(request);
        if (ret)
                return ret;