drm/nouveau/core: support multiple nvdec instances
authorBen Skeggs <bskeggs@redhat.com>
Tue, 11 Dec 2018 04:50:02 +0000 (14:50 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 11 Dec 2018 05:37:44 +0000 (15:37 +1000)
Turing GPUs can have more than one.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
drivers/gpu/drm/nouveau/nvkm/falcon/base.c
drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gp102.c
drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.c

index d83d834b745217940a9125c8ce99930aad6ac79a..feb2215f1ca7f6f9ed239f4955bef60ec384c297 100644 (file)
@@ -61,7 +61,10 @@ enum nvkm_devidx {
        NVKM_ENGINE_NVENC2,
        NVKM_ENGINE_NVENC_LAST = NVKM_ENGINE_NVENC2,
 
-       NVKM_ENGINE_NVDEC,
+       NVKM_ENGINE_NVDEC0,
+       NVKM_ENGINE_NVDEC1,
+       NVKM_ENGINE_NVDEC_LAST = NVKM_ENGINE_NVDEC1,
+
        NVKM_ENGINE_PM,
        NVKM_ENGINE_SEC,
        NVKM_ENGINE_SEC2,
@@ -163,7 +166,7 @@ struct nvkm_device {
        struct nvkm_engine *msppp;
        struct nvkm_engine *msvld;
        struct nvkm_engine *nvenc[3];
-       struct nvkm_nvdec *nvdec;
+       struct nvkm_nvdec *nvdec[2];
        struct nvkm_pm *pm;
        struct nvkm_engine *sec;
        struct nvkm_sec2 *sec2;
@@ -235,7 +238,7 @@ struct nvkm_device_chip {
        int (*msppp   )(struct nvkm_device *, int idx, struct nvkm_engine **);
        int (*msvld   )(struct nvkm_device *, int idx, struct nvkm_engine **);
        int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_engine **);
-       int (*nvdec   )(struct nvkm_device *, int idx, struct nvkm_nvdec **);
+       int (*nvdec[2])(struct nvkm_device *, int idx, struct nvkm_nvdec **);
        int (*pm      )(struct nvkm_device *, int idx, struct nvkm_pm **);
        int (*sec     )(struct nvkm_device *, int idx, struct nvkm_engine **);
        int (*sec2    )(struct nvkm_device *, int idx, struct nvkm_sec2 **);
index 03f676c18aad5240e654739d6092a62ca5f74e4f..775ab7d59533abbbec48f9c00f6c4b6ab2dace44 100644 (file)
@@ -79,7 +79,8 @@ nvkm_subdev_name[NVKM_SUBDEV_NR] = {
        [NVKM_ENGINE_NVENC0  ] = "nvenc0",
        [NVKM_ENGINE_NVENC1  ] = "nvenc1",
        [NVKM_ENGINE_NVENC2  ] = "nvenc2",
-       [NVKM_ENGINE_NVDEC   ] = "nvdec",
+       [NVKM_ENGINE_NVDEC0  ] = "nvdec0",
+       [NVKM_ENGINE_NVDEC1  ] = "nvdec1",
        [NVKM_ENGINE_PM      ] = "pm",
        [NVKM_ENGINE_SEC     ] = "sec",
        [NVKM_ENGINE_SEC2    ] = "sec2",
index e294013426ced84844d6950facd1737f63f3205c..90f4281362fcd3714f5ad4446aff6552e4427595 100644 (file)
@@ -2221,7 +2221,7 @@ nv132_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp102_gr_new,
-       .nvdec = gp102_nvdec_new,
+       .nvdec[0] = gp102_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2257,7 +2257,7 @@ nv134_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp104_gr_new,
-       .nvdec = gp102_nvdec_new,
+       .nvdec[0] = gp102_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2293,7 +2293,7 @@ nv136_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp104_gr_new,
-       .nvdec = gp102_nvdec_new,
+       .nvdec[0] = gp102_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2329,7 +2329,7 @@ nv137_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp107_gr_new,
-       .nvdec = gp102_nvdec_new,
+       .nvdec[0] = gp102_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2365,7 +2365,7 @@ nv138_chipset = {
        .dma = gf119_dma_new,
        .fifo = gp100_fifo_new,
        .gr = gp107_gr_new,
-       .nvdec = gp102_nvdec_new,
+       .nvdec[0] = gp102_nvdec_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
 };
@@ -2430,7 +2430,7 @@ nv140_chipset = {
        .dma = gv100_dma_new,
        .fifo = gv100_fifo_new,
        .gr = gv100_gr_new,
-       .nvdec = gp102_nvdec_new,
+       .nvdec[0] = gp102_nvdec_new,
        .sec2 = gp102_sec2_new,
 };
 
@@ -2529,7 +2529,8 @@ nvkm_device_engine(struct nvkm_device *device, int index)
        _(NVENC0 , device->nvenc[0],  device->nvenc[0]);
        _(NVENC1 , device->nvenc[1],  device->nvenc[1]);
        _(NVENC2 , device->nvenc[2],  device->nvenc[2]);
-       _(NVDEC  , device->nvdec   , &device->nvdec->engine);
+       _(NVDEC0 , device->nvdec[0], &device->nvdec[0]->engine);
+       _(NVDEC1 , device->nvdec[1], &device->nvdec[1]->engine);
        _(PM     , device->pm      , &device->pm->engine);
        _(SEC    , device->sec     ,  device->sec);
        _(SEC2   , device->sec2    , &device->sec2->engine);
@@ -2988,7 +2989,8 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
                _(NVKM_ENGINE_NVENC0  , nvenc[0]);
                _(NVKM_ENGINE_NVENC1  , nvenc[1]);
                _(NVKM_ENGINE_NVENC2  , nvenc[2]);
-               _(NVKM_ENGINE_NVDEC   ,    nvdec);
+               _(NVKM_ENGINE_NVDEC0  , nvdec[0]);
+               _(NVKM_ENGINE_NVDEC1  , nvdec[1]);
                _(NVKM_ENGINE_PM      ,       pm);
                _(NVKM_ENGINE_SEC     ,      sec);
                _(NVKM_ENGINE_SEC2    ,     sec2);
index dde6bbafa709f781e776434c374664dff037c9a6..91072836e8163ec2ea75aa9a8afad35e4eef8cb8 100644 (file)
@@ -91,7 +91,7 @@ nvkm_udevice_info_v1(struct nvkm_device *device,
        case ENGINE_A(MSENC ); break;
        case ENGINE_A(VIC   ); break;
        case ENGINE_A(SEC2  ); break;
-       case ENGINE_A(NVDEC ); break;
+       case ENGINE_B(NVDEC ); break;
        case ENGINE_B(NVENC ); break;
        default:
                args->mthd = NV_DEVICE_INFO_INVALID;
index 118b37aea318f94b4f4af80bb476a10136b1d495..9875574589d752f0495fa8d47ad6d7cc05a71318 100644 (file)
@@ -85,7 +85,7 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
        case NVKM_ENGINE_MSVLD : return 0x0270;
        case NVKM_ENGINE_VIC   : return 0x0280;
        case NVKM_ENGINE_MSENC : return 0x0290;
-       case NVKM_ENGINE_NVDEC : return 0x02100270;
+       case NVKM_ENGINE_NVDEC0: return 0x02100270;
        case NVKM_ENGINE_NVENC0: return 0x02100290;
        case NVKM_ENGINE_NVENC1: return 0x0210;
        default:
index 14be41f24155a737a1eff869f5778380fae803c4..427340153640111c8c1b418000df37ff31a85785 100644 (file)
@@ -197,7 +197,7 @@ nvkm_falcon_ctor(const struct nvkm_falcon_func *func,
        case NVKM_SUBDEV_PMU:
                debug_reg = 0xc08;
                break;
-       case NVKM_ENGINE_NVDEC:
+       case NVKM_ENGINE_NVDEC0:
                debug_reg = 0xd00;
                break;
        case NVKM_ENGINE_SEC2:
index 1f7a3c1a7f5061b74e89febd1213b493bacab9b6..84a2f243ed9bd16a59bf752f1f01602c72519c03 100644 (file)
@@ -59,10 +59,10 @@ gp102_run_secure_scrub(struct nvkm_secboot *sb)
 
        nvkm_debug(subdev, "running VPR scrubber binary on NVDEC...\n");
 
-       engine = nvkm_engine_ref(&device->nvdec->engine);
+       engine = nvkm_engine_ref(&device->nvdec[0]->engine);
        if (IS_ERR(engine))
                return PTR_ERR(engine);
-       falcon = device->nvdec->falcon;
+       falcon = device->nvdec[0]->falcon;
 
        nvkm_falcon_get(falcon, &sb->subdev);
 
index 4f1f3e890650601a4514e2aaa84805d346bb8d1b..39081eadfd84cd29422c612ae715593bb8940b0c 100644 (file)
@@ -86,7 +86,7 @@ gk104_top_oneinit(struct nvkm_top *top)
                case 0x0000000d: A_(SEC2  ); break;
                case 0x0000000e: B_(NVENC ); break;
                case 0x0000000f: A_(NVENC1); break;
-               case 0x00000010: A_(NVDEC ); break;
+               case 0x00000010: B_(NVDEC ); break;
                case 0x00000013: B_(CE    ); break;
                        break;
                default: