powerpc/perf: Cleanup of PM_BR_CMPL vs. PM_BRU_CMPL in Power9 event list

Fixes: 34922527a2bc ("powerpc/perf: Add power9 event list macros for generic and cache events")
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/perf/power9-events-list.h b/arch/powerpc/perf/power9-events-list.h
index 3910dd81919d81f8447b0c2cd742213f21b52eb1..e99c6bf4d391073e0fdb94c588421b8b821efab5 100644 (file)
--- a/arch/powerpc/perf/power9-events-list.h
+++ b/arch/powerpc/perf/power9-events-list.h
@@ -16,7 +16,7 @@ EVENT(PM_CYC,                                 0x0001e)
 EVENT(PM_ICT_NOSLOT_CYC,                       0x100f8)
 EVENT(PM_CMPLU_STALL,                          0x1e054)
 EVENT(PM_INST_CMPL,                            0x00002)
-EVENT(PM_BRU_CMPL,                             0x4d05e)
+EVENT(PM_BR_CMPL,                              0x4d05e)
 EVENT(PM_BR_MPRED_CMPL,                                0x400f6)
 
 /* All L1 D cache load references counted at finish, gated by reject */

diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index bbf675983f21090db23ffe77f7a5def260f653af..24b5b5b7a2064179a6e6685ee3331cf45b6861be 100644 (file)
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -128,7 +128,7 @@ GENERIC_EVENT_ATTR(cpu-cycles,                      PM_CYC);
 GENERIC_EVENT_ATTR(stalled-cycles-frontend,    PM_ICT_NOSLOT_CYC);
 GENERIC_EVENT_ATTR(stalled-cycles-backend,     PM_CMPLU_STALL);
 GENERIC_EVENT_ATTR(instructions,               PM_INST_CMPL);
-GENERIC_EVENT_ATTR(branch-instructions,                PM_BRU_CMPL);
+GENERIC_EVENT_ATTR(branch-instructions,                PM_BR_CMPL);
 GENERIC_EVENT_ATTR(branch-misses,              PM_BR_MPRED_CMPL);
 GENERIC_EVENT_ATTR(cache-references,           PM_LD_REF_L1);
 GENERIC_EVENT_ATTR(cache-misses,               PM_LD_MISS_L1_FIN);
@@ -146,7 +146,7 @@ CACHE_EVENT_ATTR(LLC-prefetches,            PM_L3_PREF_ALL);
 CACHE_EVENT_ATTR(LLC-store-misses,             PM_L2_ST_MISS);
 CACHE_EVENT_ATTR(LLC-stores,                   PM_L2_ST);
 CACHE_EVENT_ATTR(branch-load-misses,           PM_BR_MPRED_CMPL);
-CACHE_EVENT_ATTR(branch-loads,                 PM_BRU_CMPL);
+CACHE_EVENT_ATTR(branch-loads,                 PM_BR_CMPL);
 CACHE_EVENT_ATTR(dTLB-load-misses,             PM_DTLB_MISS);
 CACHE_EVENT_ATTR(iTLB-load-misses,             PM_ITLB_MISS);
 
@@ -155,7 +155,7 @@ static struct attribute *power9_events_attr[] = {
        GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
        GENERIC_EVENT_PTR(PM_CMPLU_STALL),
        GENERIC_EVENT_PTR(PM_INST_CMPL),
-       GENERIC_EVENT_PTR(PM_BRU_CMPL),
+       GENERIC_EVENT_PTR(PM_BR_CMPL),
        GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
        GENERIC_EVENT_PTR(PM_LD_REF_L1),
        GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
@@ -172,7 +172,7 @@ static struct attribute *power9_events_attr[] = {
        CACHE_EVENT_PTR(PM_L2_ST_MISS),
        CACHE_EVENT_PTR(PM_L2_ST),
        CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
-       CACHE_EVENT_PTR(PM_BRU_CMPL),
+       CACHE_EVENT_PTR(PM_BR_CMPL),
        CACHE_EVENT_PTR(PM_DTLB_MISS),
        CACHE_EVENT_PTR(PM_ITLB_MISS),
        NULL
@@ -247,7 +247,7 @@ static int power9_generic_events[] = {
        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
        [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
-       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_CMPL,
+       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BR_CMPL,
        [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
        [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
@@ -373,7 +373,7 @@ static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
        },
        [ C(BPU) ] = {
                [ C(OP_READ) ] = {
-                       [ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
+                       [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
                        [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
                },
                [ C(OP_WRITE) ] = {
@@ -462,8 +462,8 @@ static int __init init_power9_pmu(void)
                 * Power9 DD1 should use PM_BR_CMPL_ALT event code for
                 * "branches" to provide correct counter value.
                 */
-               EVENT_VAR(PM_BRU_CMPL, _g).id = PM_BR_CMPL_ALT;
-               EVENT_VAR(PM_BRU_CMPL, _c).id = PM_BR_CMPL_ALT;
+               EVENT_VAR(PM_BR_CMPL, _g).id = PM_BR_CMPL_ALT;
+               EVENT_VAR(PM_BR_CMPL, _c).id = PM_BR_CMPL_ALT;
                rc = register_power_pmu(&power9_isa207_pmu);
        } else {
                rc = register_power_pmu(&power9_pmu);