clk: samsung: exynos5420: Add more entries to EPLL rate table

Adding these EPLL output frequency entries allows to support all required
audio sample rates on the CODEC and the HDMI interface on Peach-Pit
Chromebook.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 1bb6e103509f42744347c5756073fc0c6928893a..95e1bf69449b75c1812c095f2db2483deac91dae 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
        PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
        PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
        PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
+       PLL_36XX_RATE(24 * MHZ,  73728000U, 98, 2, 4, 19923),
+       PLL_36XX_RATE(24 * MHZ,  67737602U, 90, 2, 4, 20762),
        PLL_36XX_RATE(24 * MHZ,  65536003U, 131, 3, 4, 4719),
        PLL_36XX_RATE(24 * MHZ,  49152000U, 197, 3, 5, -25690),
+       PLL_36XX_RATE(24 * MHZ,  45158401U, 90, 3, 4, 20762),
        PLL_36XX_RATE(24 * MHZ,  32768001U, 131, 3, 5, 4719),
 };