RISC-V: Add the directive for alignment of stvec's value

The stvec's value must be 4 byte alignment by specification definition.
These directives avoid to stvec be set the non-alignment value.

Signed-off-by: Zong Li <zong@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 6e07ed37bbff794bb52664670b42c10c59810e01..c4d2c63f9a2927396f2d47c23e35a9fdedcd21f9 100644 (file)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -94,6 +94,7 @@ relocate:
        or a0, a0, a1
        sfence.vma
        csrw sptbr, a0
+.align 2
 1:
        /* Set trap vector to spin forever to help debug */
        la a0, .Lsecondary_park
@@ -143,6 +144,7 @@ relocate:
        tail smp_callin
 #endif
 
+.align 2
 .Lsecondary_park:
        /* We lack SMP support or have too many harts, so park this hart */
        wfi