[PARISC] Properly specify index field to I/D cache flush ops

replace use of "0" with "%r0" since PA 1.1 I/D flush ops only take a
general register and not an immediate value for the index field.
This just forces the code to always be PA 1.1 "clean".

From: Joel Soete <soete.joel@tiscali.be>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>

diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index e217ae369fbb9d1223a0c7c19761d260e718f8e6..08cde5addfca7409b77e4c10403567eb45c8261e 100644 (file)
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -227,7 +227,7 @@ flush_instruction_cache_local:
 
 fimanyloop:                                    /* Loop if LOOP >= 2 */
        ADDIB>          -1, %r31, fimanyloop    /* Adjusted inner loop decr */
-       fice            0(%sr1, %arg0)
+       fice            %r0(%sr1, %arg0)
        fice,m          %arg1(%sr1, %arg0)      /* Last fice and addr adjust */
        movb,tr         %arg3, %r31, fimanyloop /* Re-init inner loop count */
        ADDIB<=,n       -1, %arg2, fisync       /* Outer loop decr */
@@ -269,7 +269,7 @@ flush_data_cache_local:
 
 fdmanyloop:                                    /* Loop if LOOP >= 2 */
        ADDIB>          -1, %r31, fdmanyloop    /* Adjusted inner loop decr */
-       fdce            0(%sr1, %arg0)
+       fdce            %r0(%sr1, %arg0)
        fdce,m          %arg1(%sr1, %arg0)      /* Last fdce and addr adjust */
        movb,tr         %arg3, %r31, fdmanyloop /* Re-init inner loop count */
        ADDIB<=,n       -1, %arg2, fdsync       /* Outer loop decr */

diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index befdfe70061666f17f1abaeb3de375136ab0b6d1..82c24e62ab631f7bd57bb187f946238e235cae20 100644 (file)
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -625,11 +625,14 @@ do_signal(sigset_t *oldset, struct pt_regs *regs, int in_syscall)
                        put_user(0xe0008200, &usp[3]);
                        put_user(0x34140000, &usp[4]);
 
-                       /* Stack is 64-byte aligned, and we only 
-                        * need to flush 1 cache line */
-                       asm("fdc 0(%%sr3, %0)\n"
+                       /* Stack is 64-byte aligned, and we only need
+                        * to flush 1 cache line.
+                        * Flushing one cacheline is cheap.
+                        * "sync" on bigger (> 4 way) boxes is not.
+                        */
+                       asm("fdc %%r0(%%sr3, %0)\n"
                            "sync\n"
-                           "fic 0(%%sr3, %0)\n"
+                           "fic %%r0(%%sr3, %0)\n"
                            "sync\n"
                            : : "r"(regs->gr[30]));