switch (variant) {
case ni_gpct_variant_e_series:
return 0;
- break;
case ni_gpct_variant_m_series:
return Gi_M_Series_Alternate_Sync_Bit;
- break;
case ni_gpct_variant_660x:
return Gi_660x_Alternate_Sync_Bit;
- break;
default:
BUG();
break;
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
- break;
case ni_gpct_variant_m_series:
return Gi_M_Series_Prescale_X2_Bit;
- break;
case ni_gpct_variant_660x:
return Gi_660x_Prescale_X2_Bit;
- break;
default:
BUG();
break;
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
- break;
case ni_gpct_variant_m_series:
return Gi_M_Series_Prescale_X8_Bit;
- break;
case ni_gpct_variant_660x:
return Gi_660x_Prescale_X8_Bit;
- break;
default:
BUG();
break;
switch (variant) {
case ni_gpct_variant_e_series:
return 0;
- break;
case ni_gpct_variant_m_series:
return Gi_M_Series_HW_Arm_Select_Mask;
- break;
case ni_gpct_variant_660x:
return Gi_660x_HW_Arm_Select_Mask;
- break;
default:
BUG();
break;
switch (counter_dev->variant) {
case ni_gpct_variant_e_series:
return 0;
- break;
case ni_gpct_variant_m_series:
case ni_gpct_variant_660x:
return 1;
- break;
default:
BUG();
break;
/* Gi_Source_Subselect doesn't matter */
default:
return;
- break;
}
write_register(counter, counter_dev->regs[second_gate_reg],
second_gate_reg);
break;
default:
return -EINVAL;
- break;
}
ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
Gi_Prescale_X2_Bit(counter_dev->variant) |
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
return ni_m_series_clock_src_select(counter);
- break;
case ni_gpct_variant_660x:
return ni_660x_clock_src_select(counter);
- break;
default:
BUG();
break;
default:
/* clock period is specified by user with prescaling already taken into account. */
return counter->clock_period_ps;
- break;
}
switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
if (i <= ni_660x_max_gate_pin)
break;
return -EINVAL;
- break;
}
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
Gi_Gate_Select_Mask,
if (i <= ni_m_series_max_pfi_channel)
break;
return -EINVAL;
- break;
}
ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
Gi_Gate_Select_Mask,
if (i <= ni_660x_max_up_down_pin)
break;
return -EINVAL;
- break;
}
counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
case ni_gpct_variant_e_series:
case ni_gpct_variant_m_series:
return ni_m_series_set_first_gate(counter, gate_source);
- break;
case ni_gpct_variant_660x:
return ni_660x_set_first_gate(counter, gate_source);
- break;
default:
BUG();
break;
case ni_gpct_variant_m_series:
return ni_m_series_set_second_gate(counter,
gate_source);
- break;
case ni_gpct_variant_660x:
return ni_660x_set_second_gate(counter, gate_source);
- break;
default:
BUG();
break;
break;
default:
return -EINVAL;
- break;
}
return 0;
}
break;
default:
return -EINVAL;
- break;
}
mask = 0x1f << shift;
if (source > 0x1f) {
switch (ni_660x_gate_select) {
case NI_660x_Source_Pin_i_Gate_Select:
return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
- break;
case NI_660x_Gate_Pin_i_Gate_Select:
return NI_GPCT_GATE_PIN_i_GATE_SELECT;
- break;
case NI_660x_Next_SRC_Gate_Select:
return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
- break;
case NI_660x_Next_Out_Gate_Select:
return NI_GPCT_NEXT_OUT_GATE_SELECT;
- break;
case NI_660x_Logic_Low_Gate_Select:
return NI_GPCT_LOGIC_LOW_GATE_SELECT;
- break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (ni_660x_gate_select == NI_660x_RTSI_Gate_Select(i)) {
return NI_GPCT_RTSI_GATE_SELECT(i);
- break;
}
}
if (i <= ni_660x_max_rtsi_channel)
if (ni_660x_gate_select ==
NI_660x_Gate_Pin_Gate_Select(i)) {
return NI_GPCT_GATE_PIN_GATE_SELECT(i);
- break;
}
}
if (i <= ni_660x_max_gate_pin)
switch (ni_m_series_gate_select) {
case NI_M_Series_Timestamp_Mux_Gate_Select:
return NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
- break;
case NI_M_Series_AI_START2_Gate_Select:
return NI_GPCT_AI_START2_GATE_SELECT;
- break;
case NI_M_Series_PXI_Star_Trigger_Gate_Select:
return NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
- break;
case NI_M_Series_Next_Out_Gate_Select:
return NI_GPCT_NEXT_OUT_GATE_SELECT;
- break;
case NI_M_Series_AI_START1_Gate_Select:
return NI_GPCT_AI_START1_GATE_SELECT;
- break;
case NI_M_Series_Next_SRC_Gate_Select:
return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
- break;
case NI_M_Series_Analog_Trigger_Out_Gate_Select:
return NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
- break;
case NI_M_Series_Logic_Low_Gate_Select:
return NI_GPCT_LOGIC_LOW_GATE_SELECT;
- break;
default:
for (i = 0; i <= ni_m_series_max_rtsi_channel; ++i) {
if (ni_m_series_gate_select ==
NI_M_Series_RTSI_Gate_Select(i)) {
return NI_GPCT_RTSI_GATE_SELECT(i);
- break;
}
}
if (i <= ni_m_series_max_rtsi_channel)
if (ni_m_series_gate_select ==
NI_M_Series_PFI_Gate_Select(i)) {
return NI_GPCT_PFI_GATE_SELECT(i);
- break;
}
}
if (i <= ni_m_series_max_pfi_channel)
switch (ni_660x_gate_select) {
case NI_660x_Source_Pin_i_Second_Gate_Select:
return NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
- break;
case NI_660x_Up_Down_Pin_i_Second_Gate_Select:
return NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
- break;
case NI_660x_Next_SRC_Second_Gate_Select:
return NI_GPCT_NEXT_SOURCE_GATE_SELECT;
- break;
case NI_660x_Next_Out_Second_Gate_Select:
return NI_GPCT_NEXT_OUT_GATE_SELECT;
- break;
case NI_660x_Selected_Gate_Second_Gate_Select:
return NI_GPCT_SELECTED_GATE_GATE_SELECT;
- break;
case NI_660x_Logic_Low_Second_Gate_Select:
return NI_GPCT_LOGIC_LOW_GATE_SELECT;
- break;
default:
for (i = 0; i <= ni_660x_max_rtsi_channel; ++i) {
if (ni_660x_gate_select ==
NI_660x_RTSI_Second_Gate_Select(i)) {
return NI_GPCT_RTSI_GATE_SELECT(i);
- break;
}
}
if (i <= ni_660x_max_rtsi_channel)
if (ni_660x_gate_select ==
NI_660x_Up_Down_Pin_Second_Gate_Select(i)) {
return NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
- break;
}
}
if (i <= ni_660x_max_up_down_pin)
switch (ni_m_series_gate_select) {
default:
return ni_m_series_gate_select;
- break;
}
return 0;
};
break;
default:
return -EINVAL;
- break;
}
return 0;
}
switch (data[0]) {
case INSN_CONFIG_SET_COUNTER_MODE:
return ni_tio_set_counter_mode(counter, data[1]);
- break;
case INSN_CONFIG_ARM:
return ni_tio_arm(counter, 1, data[1]);
- break;
case INSN_CONFIG_DISARM:
ni_tio_arm(counter, 0, 0);
return 0;
- break;
case INSN_CONFIG_GET_COUNTER_STATUS:
data[1] = ni_tio_counter_status(counter);
data[2] = counter_status_mask;
return 0;
- break;
case INSN_CONFIG_SET_CLOCK_SRC:
return ni_tio_set_clock_src(counter, data[1], data[2]);
- break;
case INSN_CONFIG_GET_CLOCK_SRC:
ni_tio_get_clock_src(counter, &data[1], &data[2]);
return 0;
- break;
case INSN_CONFIG_SET_GATE_SRC:
return ni_tio_set_gate_src(counter, data[1], data[2]);
- break;
case INSN_CONFIG_GET_GATE_SRC:
return ni_tio_get_gate_src(counter, data[1], &data[2]);
- break;
case INSN_CONFIG_SET_OTHER_SRC:
return ni_tio_set_other_src(counter, data[1], data[2]);
- break;
case INSN_CONFIG_RESET:
ni_tio_reset_count_and_disarm(counter);
return 0;
- break;
default:
break;
}
correct_read = first_read;
data[0] = correct_read;
return 0;
- break;
case 1:
data[0] = counter_dev->regs[NITIO_LOADA_REG(cidx)];
break;
break;
default:
return -EINVAL;
- break;
}
return 0;
}