#define AI_BUFFER_SIZE 1024 /* max ai fifo size */
#define AO_BUFFER_SIZE 1024 /* max ao fifo size */
-/* Control/Status registers */
+/*
+ * PCI BAR1 Register map (devpriv->pcibar1)
+ */
#define INT_ADCFIFO 0 /* INTERRUPT / ADC FIFO register */
#define INT_EOS 0x1 /* int end of scan */
#define INT_FHF 0x2 /* int fifo half full */
struct comedi_8254 *ao_pacer;
/* base addresses */
unsigned long s5933_config;
- unsigned long control_status;
+ unsigned long pcibar1;
unsigned long adc_fifo;
unsigned long ao_registers;
/* bits to write to registers */
struct cb_pcidas_private *devpriv = dev->private;
unsigned int status;
- status = inw(devpriv->control_status + ADCMUX_CONT);
+ status = inw(devpriv->pcibar1 + ADCMUX_CONT);
if (status & EOC)
return 0;
return -EBUSY;
/* enable calibration input if appropriate */
if (insn->chanspec & CR_ALT_SOURCE) {
outw(cal_enable_bits(dev),
- devpriv->control_status + CALIBRATION_REG);
+ devpriv->pcibar1 + CALIBRATION_REG);
chan = 0;
} else {
- outw(0, devpriv->control_status + CALIBRATION_REG);
+ outw(0, devpriv->pcibar1 + CALIBRATION_REG);
}
/* set mux limits and gain */
/* set single-ended/differential */
if (aref != AREF_DIFF)
bits |= SE;
- outw(bits, devpriv->control_status + ADCMUX_CONT);
+ outw(bits, devpriv->pcibar1 + ADCMUX_CONT);
/* clear fifo */
outw(0, devpriv->adc_fifo + ADCFIFOCLR);
devpriv->ao_control_bits &= (~DAC_MODE_UPDATE_BOTH &
~DAC_RANGE_MASK(chan));
devpriv->ao_control_bits |= (DACEN | DAC_RANGE(chan, range));
- outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR);
+ outw(devpriv->ao_control_bits, devpriv->pcibar1 + DAC_CSR);
spin_unlock_irqrestore(&dev->spinlock, flags);
/* remember value for readback */
~DAC_RANGE_MASK(chan) & ~DAC_PACER_MASK);
devpriv->ao_control_bits |= (DACEN | DAC_RANGE(chan, range) |
DAC_CHAN_EN(chan) | DAC_START);
- outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR);
+ outw(devpriv->ao_control_bits, devpriv->pcibar1 + DAC_CSR);
spin_unlock_irqrestore(&dev->spinlock, flags);
/* remember value for readback */
else
register_bits &= ~SERIAL_DATA_IN_BIT;
udelay(write_delay);
- outw(register_bits, devpriv->control_status + CALIBRATION_REG);
+ outw(register_bits, devpriv->pcibar1 + CALIBRATION_REG);
}
}
udelay(caldac_8800_udelay);
outw(cal_enable_bits(dev) | SELECT_8800_BIT,
- devpriv->control_status + CALIBRATION_REG);
+ devpriv->pcibar1 + CALIBRATION_REG);
udelay(caldac_8800_udelay);
- outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG);
+ outw(cal_enable_bits(dev), devpriv->pcibar1 + CALIBRATION_REG);
}
static int cb_pcidas_caldac_insn_write(struct comedi_device *dev,
value |= cal_enable_bits(dev);
/* latch the new value into the caldac */
- outw(value, devpriv->control_status + CALIBRATION_REG);
+ outw(value, devpriv->pcibar1 + CALIBRATION_REG);
udelay(1);
outw(value | SELECT_DAC08_BIT,
- devpriv->control_status + CALIBRATION_REG);
+ devpriv->pcibar1 + CALIBRATION_REG);
udelay(1);
- outw(value, devpriv->control_status + CALIBRATION_REG);
+ outw(value, devpriv->pcibar1 + CALIBRATION_REG);
udelay(1);
}
register_bits = cal_enable_bits(dev) | SELECT_TRIMPOT_BIT;
udelay(ad7376_udelay);
- outw(register_bits, devpriv->control_status + CALIBRATION_REG);
+ outw(register_bits, devpriv->pcibar1 + CALIBRATION_REG);
write_calibration_bitstream(dev, register_bits, bitstream,
bitstream_length);
udelay(ad7376_udelay);
- outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG);
+ outw(cal_enable_bits(dev), devpriv->pcibar1 + CALIBRATION_REG);
return 0;
}
register_bits = cal_enable_bits(dev) | SELECT_TRIMPOT_BIT;
udelay(ad8402_udelay);
- outw(register_bits, devpriv->control_status + CALIBRATION_REG);
+ outw(register_bits, devpriv->pcibar1 + CALIBRATION_REG);
write_calibration_bitstream(dev, register_bits, bitstream,
bitstream_length);
udelay(ad8402_udelay);
- outw(cal_enable_bits(dev), devpriv->control_status + CALIBRATION_REG);
+ outw(cal_enable_bits(dev), devpriv->pcibar1 + CALIBRATION_REG);
return 0;
}
unsigned long flags;
/* make sure CAL_EN_BIT is disabled */
- outw(0, devpriv->control_status + CALIBRATION_REG);
+ outw(0, devpriv->pcibar1 + CALIBRATION_REG);
/* initialize before settings pacer source and count values */
- outw(0, devpriv->control_status + TRIG_CONTSTAT);
+ outw(0, devpriv->pcibar1 + TRIG_CONTSTAT);
/* clear fifo */
outw(0, devpriv->adc_fifo + ADCFIFOCLR);
bits |= PACER_EXT_RISE;
else
bits |= PACER_INT;
- outw(bits, devpriv->control_status + ADCMUX_CONT);
+ outw(bits, devpriv->pcibar1 + ADCMUX_CONT);
/* load counters */
if (cmd->scan_begin_src == TRIG_TIMER ||
/* enable (and clear) interrupts */
outw(devpriv->adc_fifo_bits | EOAI | INT | LADFUL,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
/* set start trigger and burst mode */
}
if (cmd->convert_src == TRIG_NOW && cmd->chanlist_len > 1)
bits |= BURSTE;
- outw(bits, devpriv->control_status + TRIG_CONTSTAT);
+ outw(bits, devpriv->pcibar1 + TRIG_CONTSTAT);
return 0;
}
spin_lock_irqsave(&dev->spinlock, flags);
/* disable interrupts */
devpriv->adc_fifo_bits &= ~INTE & ~EOAIE;
- outw(devpriv->adc_fifo_bits, devpriv->control_status + INT_ADCFIFO);
+ outw(devpriv->adc_fifo_bits, devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
/* disable start trigger source and burst mode */
- outw(0, devpriv->control_status + TRIG_CONTSTAT);
+ outw(0, devpriv->pcibar1 + TRIG_CONTSTAT);
/* software pacer source */
- outw(0, devpriv->control_status + ADCMUX_CONT);
+ outw(0, devpriv->pcibar1 + ADCMUX_CONT);
return 0;
}
/* enable and clear interrupts */
outw(devpriv->adc_fifo_bits | DAEMI | DAHFI,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
/* start dac */
devpriv->ao_control_bits |= DAC_START | DACEN | DAC_EMPTY;
- outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR);
+ outw(devpriv->ao_control_bits, devpriv->pcibar1 + DAC_CSR);
spin_unlock_irqrestore(&dev->spinlock, flags);
}
/* disable analog out before settings pacer source and count values */
- outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR);
+ outw(devpriv->ao_control_bits, devpriv->pcibar1 + DAC_CSR);
spin_unlock_irqrestore(&dev->spinlock, flags);
/* clear fifo */
spin_lock_irqsave(&dev->spinlock, flags);
/* disable interrupts */
devpriv->adc_fifo_bits &= ~DAHFIE & ~DAEMIE;
- outw(devpriv->adc_fifo_bits, devpriv->control_status + INT_ADCFIFO);
+ outw(devpriv->adc_fifo_bits, devpriv->pcibar1 + INT_ADCFIFO);
/* disable output */
devpriv->ao_control_bits &= ~DACEN & ~DAC_PACER_MASK;
- outw(devpriv->ao_control_bits, devpriv->control_status + DAC_CSR);
+ outw(devpriv->ao_control_bits, devpriv->pcibar1 + DAC_CSR);
spin_unlock_irqrestore(&dev->spinlock, flags);
return 0;
/* clear dac empty interrupt latch */
spin_lock_irqsave(&dev->spinlock, flags);
outw(devpriv->adc_fifo_bits | DAEMI,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
if (inw(devpriv->ao_registers + DAC_CSR) & DAC_EMPTY) {
if (cmd->stop_src == TRIG_COUNT &&
/* clear half-full interrupt latch */
spin_lock_irqsave(&dev->spinlock, flags);
outw(devpriv->adc_fifo_bits | DAHFI,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
}
outl(devpriv->s5933_intcsr_bits | INTCSR_INBOX_INTR_STATUS,
devpriv->s5933_config + AMCC_OP_REG_INTCSR);
- status = inw(devpriv->control_status + INT_ADCFIFO);
+ status = inw(devpriv->pcibar1 + INT_ADCFIFO);
/* check for analog output interrupt */
if (status & (DAHFI | DAEMI))
/* clear half-full interrupt latch */
spin_lock_irqsave(&dev->spinlock, flags);
outw(devpriv->adc_fifo_bits | INT,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
/* else if fifo not empty */
} else if (status & (ADNEI | EOBI)) {
unsigned short val;
/* break if fifo is empty */
- if ((ADNE & inw(devpriv->control_status +
+ if ((ADNE & inw(devpriv->pcibar1 +
INT_ADCFIFO)) == 0)
break;
val = inw(devpriv->adc_fifo);
/* clear not-empty interrupt latch */
spin_lock_irqsave(&dev->spinlock, flags);
outw(devpriv->adc_fifo_bits | INT,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
} else if (status & EOAI) {
dev_err(dev->class_dev,
/* clear EOA interrupt latch */
spin_lock_irqsave(&dev->spinlock, flags);
outw(devpriv->adc_fifo_bits | EOAI,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
}
/* check for fifo overflow */
/* clear overflow interrupt latch */
spin_lock_irqsave(&dev->spinlock, flags);
outw(devpriv->adc_fifo_bits | LADFUL,
- devpriv->control_status + INT_ADCFIFO);
+ devpriv->pcibar1 + INT_ADCFIFO);
spin_unlock_irqrestore(&dev->spinlock, flags);
async->events |= COMEDI_CB_ERROR;
}
return ret;
devpriv->s5933_config = pci_resource_start(pcidev, 0);
- devpriv->control_status = pci_resource_start(pcidev, 1);
+ devpriv->pcibar1 = pci_resource_start(pcidev, 1);
devpriv->adc_fifo = pci_resource_start(pcidev, 2);
dev->iobase = pci_resource_start(pcidev, 3);
if (board->has_ao)