Also fixes some GPUs where we write too many registers.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
gf100_grctx_generate_r4060a8(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
- u8 tpcnr[GPC_MAX], data[TPC_MAX];
+ const u8 gpcmax = nvkm_rd32(device, 0x022430);
+ const u8 tpcmax = nvkm_rd32(device, 0x022434) * gpcmax;
+ u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));
data[tpc] = gpc;
}
- for (i = 0; i < 4; i++)
+ for (i = 0; i < DIV_ROUND_UP(tpcmax, 4); i++)
nvkm_wr32(device, 0x4060a8 + (i * 4), ((u32 *)data)[i]);
}
nvkm_wr32(device, 0x406028 + (i * 4), data);
nvkm_wr32(device, 0x405870 + (i * 4), data);
}
+
+ if (func->r4060a8)
+ func->r4060a8(gr);
}
void
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
- gf100_grctx_generate_r4060a8(gr);
gf100_grctx_generate_r418bb8(gr);
gf100_grctx_generate_r406800(gr);
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
+ .r4060a8 = gf100_grctx_generate_r4060a8,
};
/* floorsweeping */
void (*sm_id)(struct gf100_gr *, int gpc, int tpc, int sm);
void (*tpc_nr)(struct gf100_gr *, int gpc);
+ void (*r4060a8)(struct gf100_gr *);
};
extern const struct gf100_grctx_func gf100_grctx;
void gf100_grctx_generate_attrib(struct gf100_grctx *);
void gf100_grctx_generate_unkn(struct gf100_gr *);
void gf100_grctx_generate_floorsweep(struct gf100_gr *);
-void gf100_grctx_generate_r4060a8(struct gf100_gr *);
void gf100_grctx_generate_r418bb8(struct gf100_gr *);
void gf100_grctx_generate_r406800(struct gf100_gr *);
void gf100_grctx_generate_sm_id(struct gf100_gr *, int, int, int);
void gf100_grctx_generate_tpc_nr(struct gf100_gr *, int);
+void gf100_grctx_generate_r4060a8(struct gf100_gr *);
extern const struct gf100_grctx_func gf108_grctx;
void gf108_grctx_generate_attrib(struct gf100_grctx *);
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
+ .r4060a8 = gf100_grctx_generate_r4060a8,
};
.alpha_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
+ .r4060a8 = gf100_grctx_generate_r4060a8,
};
.attrib_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
+ .r4060a8 = gf100_grctx_generate_r4060a8,
};
grctx->unkn(gr);
gf100_grctx_generate_floorsweep(gr);
- gf100_grctx_generate_r4060a8(gr);
gk104_grctx_generate_r418bb8(gr);
gf100_grctx_generate_r406800(gr);
.alpha_nr = 0x324,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
+ .r4060a8 = gf100_grctx_generate_r4060a8,
};
.alpha_nr = 0x218,
.sm_id = gf100_grctx_generate_sm_id,
.tpc_nr = gf100_grctx_generate_tpc_nr,
+ .r4060a8 = gf100_grctx_generate_r4060a8,
};