drm/msm/a6xx: Send the right perf index value to GMU

The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index bbb8126ec5c573ba7d58610832606e3eaa18410c..bfa3f468a31c389beb573aecfc2f1a8ef253ffb8 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -70,7 +70,7 @@ static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index)
        gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
 
        gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
-               ((index << 24) & 0xff) | (3 & 0xf));
+               ((3 & 0xf) << 28) | index);
 
        /*
         * Send an invalid index as a vote for the bus bandwidth and let the