clk: imx7d: Correct ahb clk parent select

Design team change the ahb's clk parent options but
did NOT update the DOC accordingly in time, so the
AHB/IPG's clk rate in clk tree is incorrect, AHB is
67.5MHz and IPG is 33.75MHz, but using scope to
monitor them, they are actually 135MHz and 67.5MHz,
update the clk parent option to make clk tree info
correct.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Irina Tirdea <irina.tirdea@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 1cc485f6c621723af188e81c512876a645e3c937..50da4cb0091248bbdeb9aaae95b931e570410447 100644 (file)
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -74,7 +74,7 @@ static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
 
 static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
        "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
-       "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div",
+       "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
        "pll_video_post_div", };
 
 static const char *dram_phym_sel[] = { "pll_dram_main_clk",