drm/i915: Convert i915_gem_flush_ggtt_writes to intel_gt

Having introduced struct intel_gt (named the anonymous structure in i915)
we can start using it to compartmentalize our code better. It makes more
sense logically to have the code internally like this and it will also
help with future split between gt and display in i915.

v2:
 * Keep ggtt flush before fb obj flush. (Chris)

v3:
 * Fix refactoring fail.
 * Always flush ggtt writes. (Chris)

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190621070811.7006-23-tvrtko.ursulin@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index be6caccce0c5e0fd31a441e34bc89833c290dd21..87275f9883ac30933fb30c657d8b3ac3de968b15 100644 (file)
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -23,7 +23,7 @@
  */
 
 #include "display/intel_frontbuffer.h"
-
+#include "gt/intel_gt.h"
 #include "i915_drv.h"
 #include "i915_gem_clflush.h"
 #include "i915_gem_context.h"
@@ -319,7 +319,6 @@ void
 i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
                                   unsigned int flush_domains)
 {
-       struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
        struct i915_vma *vma;
 
        assert_object_held(obj);
@@ -329,7 +328,8 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 
        switch (obj->write_domain) {
        case I915_GEM_DOMAIN_GTT:
-               i915_gem_flush_ggtt_writes(dev_priv);
+               for_each_ggtt_vma(vma, obj)
+                       intel_gt_flush_ggtt_writes(vma->vm->gt);
 
                intel_fb_obj_flush(obj,
                                   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
@@ -340,6 +340,7 @@ i915_gem_object_flush_write_domain(struct drm_i915_gem_object *obj,
 
                        i915_vma_unset_ggtt_write(vma);
                }
+
                break;
 
        case I915_GEM_DOMAIN_WC:

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 5c81f4b4813a01ffc1645a4650e61cd0c84cbde8..2812f7fa27fe52f8b18b3f56ea69f24e0adf2ca6 100644 (file)
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -6,6 +6,7 @@
 
 #include <linux/prime_numbers.h>
 
+#include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
 #include "huge_gem_object.h"
 #include "i915_selftest.h"
@@ -143,7 +144,7 @@ static int check_partial_mapping(struct drm_i915_gem_object *obj,
                if (offset >= obj->base.size)
                        continue;
 
-               i915_gem_flush_ggtt_writes(to_i915(obj->base.dev));
+               intel_gt_flush_ggtt_writes(&to_i915(obj->base.dev)->gt);
 
                p = i915_gem_object_get_page(obj, offset >> PAGE_SHIFT);
                cpu = kmap(p) + offset_in_page(offset);

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5c9be38713db531ff725dbc93fb8a2c24219fb29..4fd9977fe284808fcba1b8ffe9a21de6903da424 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -150,3 +150,44 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
 
        intel_gt_clear_error_registers(gt, ALL_ENGINES);
 }
+
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt)
+{
+       struct drm_i915_private *i915 = gt->i915;
+       intel_wakeref_t wakeref;
+
+       /*
+        * No actual flushing is required for the GTT write domain for reads
+        * from the GTT domain. Writes to it "immediately" go to main memory
+        * as far as we know, so there's no chipset flush. It also doesn't
+        * land in the GPU render cache.
+        *
+        * However, we do have to enforce the order so that all writes through
+        * the GTT land before any writes to the device, such as updates to
+        * the GATT itself.
+        *
+        * We also have to wait a bit for the writes to land from the GTT.
+        * An uncached read (i.e. mmio) seems to be ideal for the round-trip
+        * timing. This issue has only been observed when switching quickly
+        * between GTT writes and CPU reads from inside the kernel on recent hw,
+        * and it appears to only affect discrete GTT blocks (i.e. on LLC
+        * system agents we cannot reproduce this behaviour, until Cannonlake
+        * that was!).
+        */
+
+       wmb();
+
+       if (INTEL_INFO(i915)->has_coherent_ggtt)
+               return;
+
+       i915_gem_chipset_flush(i915);
+
+       with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+               struct intel_uncore *uncore = gt->uncore;
+
+               spin_lock_irq(&uncore->lock);
+               intel_uncore_posting_read_fw(uncore,
+                                            RING_HEAD(RENDER_RING_BASE));
+               spin_unlock_irq(&uncore->lock);
+       }
+}

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 033713b684bfb5b706b95515358b7f6b756704e2..6073f3617caa0f74dbe4d65b29fe6c5966130de7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -17,4 +17,6 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt);
 void intel_gt_clear_error_registers(struct intel_gt *gt,
                                    intel_engine_mask_t engine_mask);
 
+void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
+
 #endif /* __INTEL_GT_H__ */

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44196bed4d81fdd44335f5ff11323e6e87a2d2bc..1fd0a73b4b9a278e9b0f461bb733a90c0a711203 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2599,8 +2599,6 @@ int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
                                         unsigned int flags);
 int i915_gem_evict_vm(struct i915_address_space *vm);
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
-
 /* belongs in i915_gem_gtt.h */
 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
 {

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 8966f32fe2a2c2238b8992df61ab867b0d04b93b..a9189807cd7177e5fb92a45778ba8073b3115ad5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -233,46 +233,6 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data,
                               &args->size, &args->handle);
 }
 
-void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv)
-{
-       intel_wakeref_t wakeref;
-
-       /*
-        * No actual flushing is required for the GTT write domain for reads
-        * from the GTT domain. Writes to it "immediately" go to main memory
-        * as far as we know, so there's no chipset flush. It also doesn't
-        * land in the GPU render cache.
-        *
-        * However, we do have to enforce the order so that all writes through
-        * the GTT land before any writes to the device, such as updates to
-        * the GATT itself.
-        *
-        * We also have to wait a bit for the writes to land from the GTT.
-        * An uncached read (i.e. mmio) seems to be ideal for the round-trip
-        * timing. This issue has only been observed when switching quickly
-        * between GTT writes and CPU reads from inside the kernel on recent hw,
-        * and it appears to only affect discrete GTT blocks (i.e. on LLC
-        * system agents we cannot reproduce this behaviour, until Cannonlake
-        * that was!).
-        */
-
-       wmb();
-
-       if (INTEL_INFO(dev_priv)->has_coherent_ggtt)
-               return;
-
-       i915_gem_chipset_flush(dev_priv);
-
-       with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
-               struct intel_uncore *uncore = &dev_priv->uncore;
-
-               spin_lock_irq(&uncore->lock);
-               intel_uncore_posting_read_fw(uncore,
-                                            RING_HEAD(RENDER_RING_BASE));
-               spin_unlock_irq(&uncore->lock);
-       }
-}
-
 static int
 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
            bool needs_clflush)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index a57729be8312ae0903f15252170830f6c7e7950b..503f1180af12fe16bcbd4ef0dbfeeb76269023eb 100644 (file)
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -27,6 +27,7 @@
 #include "display/intel_frontbuffer.h"
 
 #include "gt/intel_engine.h"
+#include "gt/intel_gt.h"
 
 #include "i915_drv.h"
 #include "i915_globals.h"
@@ -408,7 +409,7 @@ void i915_vma_flush_writes(struct i915_vma *vma)
        if (!i915_vma_has_ggtt_write(vma))
                return;
 
-       i915_gem_flush_ggtt_writes(vma->vm->i915);
+       intel_gt_flush_ggtt_writes(vma->vm->gt);
 
        i915_vma_unset_ggtt_write(vma);
 }

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 0c47276ed5df2b73bea3bb797e6a0923c858f16c..31a51ca1ddcbb947c9e3b7d365b08e4155ab713a 100644 (file)
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -1193,7 +1193,7 @@ static int igt_ggtt_page(void *arg)
                iowrite32(n, vaddr + n);
                io_mapping_unmap_atomic(vaddr);
        }
-       i915_gem_flush_ggtt_writes(i915);
+       intel_gt_flush_ggtt_writes(ggtt->vm.gt);
 
        i915_random_reorder(order, count, &prng);
        for (n = 0; n < count; n++) {