drm/i915: [GEN7] Use HW scheduler for fixed function shaders

This originally started as a patch from Bernard as a way of simply
setting the VS scheduler. After submitting the RFC patch, we decided to
also modify the DS scheduler. To be most explicit, I've made the patch
explicitly set all scheduler modes, and included the defines for other
modes (in case someone feels frisky later).

The rest of the story gets a bit weird. The first version of the patch
showed an almost unbelievable performance improvement. Since rebasing my
branch it appears the performance improvement has gone, unfortunately.
But setting these bits seem to be the right thing to do given that the
docs describe corruption that can occur with the default settings.

In summary, I am seeing no more perf improvements (or regressions) in my
limited testing, but we believe this should be set to prevent rendering
corruption, therefore cc stable.

v1: Clear bit 4 also (Ken + Eugeni)
Do a full clear + set of the bits we want (Me).

Cc: Bernard Kilarski <bernard.r.kilarski@intel.com>
Cc: stable <stable@vger.kernel.org>
Reviewed-by (RFC): Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0d3b97f016906d5b57ba3eed110a74aea21fab7e..5ac9837e49a516b8e7bbab5d632cce02ea6bcd06 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -692,6 +692,21 @@
 
 #define GEN6_BSD_RNCID                 0x12198
 
+#define GEN7_FF_THREAD_MODE            0x20a0
+#define   GEN7_FF_SCHED_MASK           0x0077070
+#define   GEN7_FF_TS_SCHED_HS1         (0x5<<16)
+#define   GEN7_FF_TS_SCHED_HS0         (0x3<<16)
+#define   GEN7_FF_TS_SCHED_LOAD_BALANCE        (0x1<<16)
+#define   GEN7_FF_TS_SCHED_HW          (0x0<<16) /* Default */
+#define   GEN7_FF_VS_SCHED_HS1         (0x5<<12)
+#define   GEN7_FF_VS_SCHED_HS0         (0x3<<12)
+#define   GEN7_FF_VS_SCHED_LOAD_BALANCE        (0x1<<12) /* Default */
+#define   GEN7_FF_VS_SCHED_HW          (0x0<<12)
+#define   GEN7_FF_DS_SCHED_HS1         (0x5<<4)
+#define   GEN7_FF_DS_SCHED_HS0         (0x3<<4)
+#define   GEN7_FF_DS_SCHED_LOAD_BALANCE        (0x1<<4)  /* Default */
+#define   GEN7_FF_DS_SCHED_HW          (0x0<<4)
+
 /*
  * Framebuffer compression (915+ only)
  */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 78179e03a901fe7a0b67b79dc2125beabc3d84cb..96fc4679d438850b299d8c78c09fe2f28c32e6c6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8937,6 +8937,18 @@ static void gen6_init_clock_gating(struct drm_device *dev)
        }
 }
 
+static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
+{
+       uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
+
+       reg &= ~GEN7_FF_SCHED_MASK;
+       reg |= GEN7_FF_TS_SCHED_HW;
+       reg |= GEN7_FF_VS_SCHED_HW;
+       reg |= GEN7_FF_DS_SCHED_HW;
+
+       I915_WRITE(GEN7_FF_THREAD_MODE, reg);
+}
+
 static void ivybridge_init_clock_gating(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -8981,6 +8993,8 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
                           DISPPLANE_TRICKLE_FEED_DISABLE);
                intel_flush_display_plane(dev_priv, pipe);
        }
+
+       gen7_setup_fixed_func_scheduler(dev_priv);
 }
 
 static void valleyview_init_clock_gating(struct drm_device *dev)