net: dsa: mv88e6xxx: add workaround for 6341 timestamping

88E6341 devices default to timestamping at the PHY, but due to a
hardware issue, timestamps via this component are unreliable. For
this family, configure the PTP hardware to force the timestamping
to occur at the MAC.

Signed-off-by: Brandon Streiff <brandon.streiff@ni.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/mv88e6xxx/hwtstamp.c b/drivers/net/dsa/mv88e6xxx/hwtstamp.c
index 1b8f79b2c939bebd1810bee7d968ebe62b89db10..b251d534b70d1c45b774c055cd5cc61366759f4c 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/hwtstamp.c
+++ b/drivers/net/dsa/mv88e6xxx/hwtstamp.c
@@ -563,6 +563,19 @@ int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip)
        if (err)
                return err;
 
+       /* 88E6341 devices default to timestamping at the PHY, but this has
+        * a hardware issue that results in unreliable timestamps. Force
+        * these devices to timestamp at the MAC.
+        */
+       if (chip->info->family == MV88E6XXX_FAMILY_6341) {
+               u16 val = MV88E6341_PTP_CFG_UPDATE |
+                         MV88E6341_PTP_CFG_MODE_IDX |
+                         MV88E6341_PTP_CFG_MODE_TS_AT_MAC;
+               err = mv88e6xxx_ptp_write(chip, MV88E6341_PTP_CFG, val);
+               if (err)
+                       return err;
+       }
+
        return 0;
 }
 

diff --git a/drivers/net/dsa/mv88e6xxx/hwtstamp.h b/drivers/net/dsa/mv88e6xxx/hwtstamp.h
index 18ff39cdab4ca1b8f1bec9e5a5aa7bb3a24dee37..bc71c9212a0813adbe0519a9a0a27ab812bfe08a 100644 (file)
--- a/drivers/net/dsa/mv88e6xxx/hwtstamp.h
+++ b/drivers/net/dsa/mv88e6xxx/hwtstamp.h
@@ -34,6 +34,15 @@
 /* Offset 0x02: Timestamp Arrival Capture Pointers */
 #define MV88E6XXX_PTP_TS_ARRIVAL_PTR   0x02
 
+/* Offset 0x07: PTP Global Configuration */
+#define MV88E6341_PTP_CFG                      0x07
+#define MV88E6341_PTP_CFG_UPDATE               0x8000
+#define MV88E6341_PTP_CFG_IDX_MASK             0x7f00
+#define MV88E6341_PTP_CFG_DATA_MASK            0x00ff
+#define MV88E6341_PTP_CFG_MODE_IDX             0x0
+#define MV88E6341_PTP_CFG_MODE_TS_AT_PHY       0x00
+#define MV88E6341_PTP_CFG_MODE_TS_AT_MAC       0x80
+
 /* Offset 0x08: PTP Interrupt Status */
 #define MV88E6XXX_PTP_IRQ_STATUS       0x08